高级FPGA设计架构、实现和优化指南

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"Advanced FPGA Design" 本书《Advanced FPGA Design》是一本专业的FPGA设计参考书籍，由国外同行总结的实用的设计手册，涵盖了硬件设计和软件设计两方面的内容。下面是对该书的知识点总结： 1. FPGA设计基础 FPGA（Field-Programmable Gate Array）是一种可编程的数字电路阵列，能够实时地重新配置逻辑电路。FPGA设计的基础知识包括数字电路、逻辑电路、编程语言等。 2. 硬件设计硬件设计是FPGA设计的核心部分，涉及到数字电路的设计、逻辑电路的实现、电路仿真等方面的内容。本书中将讲解硬件设计的基本概念、数字电路的设计方法、逻辑电路的实现方法等。 3. 软件设计软件设计是FPGA设计的另一个重要方面，涉及到软件开发、编程语言、算法设计等方面的内容。本书中将讲解软件设计的基本概念、编程语言的使用、算法设计的方法等。 4. FPGA架构设计 FPGA架构设计是FPGA设计的关键部分，涉及到FPGA的架构设计、资源分配、时序设计等方面的内容。本书中将讲解FPGA架构设计的基本概念、架构设计方法、资源分配方法等。 5. FPGA实现和优化 FPGA实现和优化是FPGA设计的最后一步，涉及到FPGA的实现、优化、测试等方面的内容。本书中将讲解FPGA实现和优化的基本概念、实现方法、优化方法等。 6. FPGA设计工具 FPGA设计工具是FPGA设计的重要辅助工具，涉及到设计软件、仿真软件、编译软件等方面的内容。本书中将讲解FPGA设计工具的基本概念、设计软件的使用、仿真软件的使用等。 7. FPGA设计流程 FPGA设计流程是FPGA设计的整个过程，涉及到需求分析、设计、实现、测试、维护等方面的内容。本书中将讲解FPGA设计流程的基本概念、设计流程的步骤、设计流程的优化方法等。本书《Advanced FPGA Design》是一本涵盖了FPGA设计的方方面面的参考书籍，对于FPGA设计的学习和研究具有重要的参考价值。

Chapter 1

Architecting Speed

Sophisticated tool optimizations are often not good enough to mee t most design

constraints if an arbitrary coding style is used. This chapter discusses the ﬁrst of

three primary physical characteristics of a digital design: speed. This chapter also

discusses methods for architectural optimization in an FPGA.

There are three primary deﬁnitions of speed depending on the context of the

problem: throughput, latency, and timing. In the context of processing data in an

FPGA, throughput refers to the amount of data that is processed per clock cycle.

A common metric for throughput is bits per second. Latency refers to the time

between data input and processed data output. The typical metric for latency will

be time or clock cycles. Timing refers to the logic delays between sequential

elements. When we say a design does not “meet timing,” we mea n that the delay

of the critical path, that is, the largest delay between ﬂip-ﬂops (composed of

combinatorial delay, clk-to-out delay, routing delay, setup timing, clock skew,

and so on) is greater than the target clock period. The standard metrics for timing

are clock period and frequency.

During the course of this chapter, we will discuss the following topics in detail:

High-throughput architectures for maximizing the number of bits per

second that can be processed by the design.

Low-latency architectures for minimizing the delay from the input of a

module to the output.

Timing optimizations to reduce the combinatorial delay of the critical path.

Adding register layers to divide combinatorial logic structures.

Parallel structures for separating sequentially executed operations into

parallel operations.

Flattening logic structures speciﬁc to priority encoded signals.

registers.

Reordering paths to divert operations in a critical path to a noncritical path.

Advanced FPGA Design. By Steve Kilts

1.1 HIGH THROUGHPUT

A high-throughput design is one that is concerned with the steady-state data rate

but less concerned about the time any speciﬁc piece of data requires to propagate

through the design (latency). The idea with a high-throughput design is the same

idea Ford came up with to manufacture automobiles in great quantities: an assem-

bly line. In the world of digital design where data is processed, we refer to this

under a more abstract term: pipeline.

A pipelined design conceptually works very similar to an assembly line in

that the raw material or data input enters the front end, is passed through various

stages of manipulation and processing, and then exits as a ﬁnished product or data

output. The beauty of a pipelined design is that new data can begin processing

before the prior data has ﬁnished, much like cars are processed on an assembly

line. Pipelines are used in nearly all very-high-performance devices, and the

variety of speciﬁc architectures is unlimited. Examples include CPU instruction

sets, network protocol stacks, encryption engines, and so on.

From an algorithmic perspective, an important concept in a pipelined design

is that of “unrolling the loop.” As an example, consider the following piece of

code that would most likely be used in a software implementation for ﬁnding the

third power of X. Note that the term “software” here refers to code that is targeted

at a set of procedural instructions that will be executed on a microprocessor.

XPower = 1;

for (i=0;i < 3; i++)

XPower = X * XPower;

Note that the above code is an iterative algorithm. The same variables and

addresses are accessed until the computation is complete. There is no use for par-

allelism because a microprocessor only executes one instruction at a time (for the

purpose of argument, just consider a single core processor). A similar implemen-

tation can be created in hardware. Consider the following Verilo g implementation

of the same algorithm (output scaling not considered):

module power3(

output [7:0] XPower,

output finished,

input [7:0] X,

input clk, start); // the duration of start is a

single clock

reg [7:0] ncount;

reg [7:0] XPower;

assign finished = (ncount == 0);

always@(posedge clk)

if(start) begin

XPower <= X;

ncount <= 2;

end

2 Chapter 1 Architecting Speed

In the above implementation, the value of X is passed to both pipeline stages

where independent resources compute the corresponding multiply operation. Note

that while X is being used to calculate the ﬁnal power of 3 in the second pipeline

stage, the next value of X can be sent to the ﬁrst pipeline stage as shown in

Figure 1.2.

Both the ﬁnal calculation of X

(XPower3 resources) and the ﬁrst calculation

of the next value of X (XPower2 resources) occur simultaneously. The perform-

ance of this design is

Throughput ¼ 8/1, or 8 bits/clock

Latency ¼ 3 clocks

Timing ¼ One multiplier delay in the critical path

The throughput performance increased by a factor of 3 over the iterative

implementation. In general, if an algorithm requiring n iterative loops is

“unrolled,” the pipelined implementation will exhibit a throughput performance

increase of a factor of n. There was no penalty in terms of latency as the pipelined

implementation still required 3 clocks to propagate the ﬁnal computation. Like-

wise, there was no timing penalty as the critical path still contained only one

multiplier.

Unrolling an iterative loop increases throughput.

The penalty to pay for unrolling loops such as this is an increase in area. The

iterative implementation required a single register and multiplier (along with some

control logic not shown in the diagram), whereas the pipelined implementation

required a separate register for both X and XPower and a separate multiplier for

every pipeline stage. Optimizations for area are discussed in the Chapter 2.

The penalty for unrolling an iterative loop is a proportional increase in area.

1.2 LOW LATENCY

A low-latency design is one that passes the data from the input to the output as

quickly as possible by minimizing the intermediate processing delays. Oftentimes,

a low-latency design will require par allelisms, removal of pipelining, and logical

short cuts that may reduce the throughput or the max clock speed in a design.

Figure 1.2 Pipelined implementation.

4 Chapter 1 Architecting Speed

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