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LM3S8962微控制器数据手册
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更新于2024-07-26
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"LM3S8962 Microcontroller手册"
LM3S8962是一款微控制器,由Luminary Micro公司生产。该手册详细介绍了该微控制器的规格、功能和使用注意事项。作为一款微控制器,LM3S8962在设计时考虑了嵌入式系统的高效能和低功耗需求,适用于各种工业和消费类电子产品。
手册中的主要内容可能包括以下几个方面:
1. **产品概述**:LM3S8962微控制器的架构和主要特性,如处理能力(可能基于ARM Cortex-M3内核),内存配置(闪存和RAM大小),以及I/O端口的数量和类型。
2. **硬件接口**:详细列出微控制器支持的各种接口标准,例如UART、SPI、I2C、PWM、ADC和GPIO等,这些接口是与外部设备通信的关键。
3. **电源管理**:描述了LM3S8962如何实现低功耗运行,可能包括不同工作模式(如休眠和待机)以及动态电压和频率调整(DVFS)功能。
4. **外设和定时器**:详细介绍了微控制器内置的定时器和其他外设,这些外设可能用于中断服务、计数或生成波形。
5. **开发工具和软件支持**:手册可能会提到配套的开发环境,如IDE、编译器、调试器以及可能提供的RTOS(实时操作系统)和库函数,以帮助开发者快速进行系统集成。
6. **电气特性**:规定了微控制器的工作电压范围、电流消耗、输入/输出电平等电气参数,这对于设计电路板至关重要。
7. **封装和引脚配置**:提供微控制器封装图和引脚布局,帮助硬件工程师正确放置和连接元器件。
8. **应用示例**:可能包含一些典型的应用场景,如智能家居、自动化控制、物联网设备等,以展示LM3S8962的使用方式。
9. **安全和法规信息**:强调LM3S8962不适用于医疗、生命维持或救生应用,这通常是因为这类应用对产品的可靠性和安全性有特殊要求。
10. **法律免责声明和商标信息**:Luminary Micro明确指出,提供此文档并不授予任何知识产权许可,并且对于其产品销售和使用,不承担任何明示或暗示的保修责任。
在使用LM3S8962微控制器前,应联系当地的Luminary Micro销售办公室或分销商获取最新的规格信息,确保产品满足项目需求。此外,开发者还需要参考手册了解详细的编程指南和技术支持。
Register 32: GPIO PrimeCell Identification 3 (GPIOPCellID3), offset 0xFFC ......................................... 221
General-Purpose Timers ............................................................................................................. 222
Register 1: GPTM Configuration (GPTMCFG), offset 0x000 .............................................................. 234
Register 2: GPTM TimerA Mode (GPTMTAMR), offset 0x004 ............................................................ 235
Register 3: GPTM TimerB Mode (GPTMTBMR), offset 0x008 ............................................................ 237
Register 4: GPTM Control (GPTMCTL), offset 0x00C ........................................................................ 239
Register 5: GPTM Interrupt Mask (GPTMIMR), offset 0x018 .............................................................. 242
Register 6: GPTM Raw Interrupt Status (GPTMRIS), offset 0x01C ..................................................... 244
Register 7: GPTM Masked Interrupt Status (GPTMMIS), offset 0x020 ................................................ 245
Register 8: GPTM Interrupt Clear (GPTMICR), offset 0x024 .............................................................. 246
Register 9: GPTM TimerA Interval Load (GPTMTAILR), offset 0x028 ................................................. 248
Register 10: GPTM TimerB Interval Load (GPTMTBILR), offset 0x02C ................................................ 249
Register 11: GPTM TimerA Match (GPTMTAMATCHR), offset 0x030 ................................................... 250
Register 12: GPTM TimerB Match (GPTMTBMATCHR), offset 0x034 .................................................. 251
Register 13: GPTM TimerA Prescale (GPTMTAPR), offset 0x038 ........................................................ 252
Register 14: GPTM TimerB Prescale (GPTMTBPR), offset 0x03C ....................................................... 253
Register 15: GPTM TimerA Prescale Match (GPTMTAPMR), offset 0x040 ........................................... 254
Register 16: GPTM TimerB Prescale Match (GPTMTBPMR), offset 0x044 ........................................... 255
Register 17: GPTM TimerA (GPTMTAR), offset 0x048 ........................................................................ 256
Register 18: GPTM TimerB (GPTMTBR), offset 0x04C ....................................................................... 257
Watchdog Timer ........................................................................................................................... 258
Register 1: Watchdog Load (WDTLOAD), offset 0x000 ...................................................................... 262
Register 2: Watchdog Value (WDTVALUE), offset 0x004 ................................................................... 263
Register 3: Watchdog Control (WDTCTL), offset 0x008 ..................................................................... 264
Register 4: Watchdog Interrupt Clear (WDTICR), offset 0x00C .......................................................... 265
Register 5: Watchdog Raw Interrupt Status (WDTRIS), offset 0x010 .................................................. 266
Register 6: Watchdog Masked Interrupt Status (WDTMIS), offset 0x014 ............................................. 267
Register 7: Watchdog Test (WDTTEST), offset 0x418 ....................................................................... 268
Register 8: Watchdog Lock (WDTLOCK), offset 0xC00 ..................................................................... 269
Register 9: Watchdog Peripheral Identification 4 (WDTPeriphID4), offset 0xFD0 ................................. 270
Register 10: Watchdog Peripheral Identification 5 (WDTPeriphID5), offset 0xFD4 ................................. 271
Register 11: Watchdog Peripheral Identification 6 (WDTPeriphID6), offset 0xFD8 ................................. 272
Register 12: Watchdog Peripheral Identification 7 (WDTPeriphID7), offset 0xFDC ................................ 273
Register 13: Watchdog Peripheral Identification 0 (WDTPeriphID0), offset 0xFE0 ................................. 274
Register 14: Watchdog Peripheral Identification 1 (WDTPeriphID1), offset 0xFE4 ................................. 275
Register 15: Watchdog Peripheral Identification 2 (WDTPeriphID2), offset 0xFE8 ................................. 276
Register 16: Watchdog Peripheral Identification 3 (WDTPeriphID3), offset 0xFEC ................................. 277
Register 17: Watchdog PrimeCell Identification 0 (WDTPCellID0), offset 0xFF0 .................................... 278
Register 18: Watchdog PrimeCell Identification 1 (WDTPCellID1), offset 0xFF4 .................................... 279
Register 19: Watchdog PrimeCell Identification 2 (WDTPCellID2), offset 0xFF8 .................................... 280
Register 20: Watchdog PrimeCell Identification 3 (WDTPCellID3 ), offset 0xFFC .................................. 281
Analog-to-Digital Converter (ADC) ............................................................................................. 282
Register 1: ADC Active Sample Sequencer (ADCACTSS), offset 0x000 ............................................. 291
Register 2: ADC Raw Interrupt Status (ADCRIS), offset 0x004 ........................................................... 292
Register 3: ADC Interrupt Mask (ADCIM), offset 0x008 ..................................................................... 293
Register 4: ADC Interrupt Status and Clear (ADCISC), offset 0x00C .................................................. 294
Register 5: ADC Overflow Status (ADCOSTAT), offset 0x010 ............................................................ 296
Register 6: ADC Event Multiplexer Select (ADCEMUX), offset 0x014 ................................................. 297
April 01, 200916
Preliminary
Table of Contents
Register 7: ADC Underflow Status (ADCUSTAT), offset 0x018 ........................................................... 300
Register 8: ADC Sample Sequencer Priority (ADCSSPRI), offset 0x020 ............................................. 301
Register 9: ADC Processor Sample Sequence Initiate (ADCPSSI), offset 0x028 ................................. 303
Register 10: ADC Sample Averaging Control (ADCSAC), offset 0x030 ................................................. 304
Register 11: ADC Sample Sequence Input Multiplexer Select 0 (ADCSSMUX0), offset 0x040 ............... 305
Register 12: ADC Sample Sequence Control 0 (ADCSSCTL0), offset 0x044 ........................................ 307
Register 13: ADC Sample Sequence Result FIFO 0 (ADCSSFIFO0), offset 0x048 ................................ 310
Register 14: ADC Sample Sequence Result FIFO 1 (ADCSSFIFO1), offset 0x068 ................................ 310
Register 15: ADC Sample Sequence Result FIFO 2 (ADCSSFIFO2), offset 0x088 ................................ 310
Register 16: ADC Sample Sequence Result FIFO 3 (ADCSSFIFO3), offset 0x0A8 ............................... 310
Register 17: ADC Sample Sequence FIFO 0 Status (ADCSSFSTAT0), offset 0x04C ............................. 311
Register 18: ADC Sample Sequence FIFO 1 Status (ADCSSFSTAT1), offset 0x06C ............................. 311
Register 19: ADC Sample Sequence FIFO 2 Status (ADCSSFSTAT2), offset 0x08C ............................ 311
Register 20: ADC Sample Sequence FIFO 3 Status (ADCSSFSTAT3), offset 0x0AC ............................ 311
Register 21: ADC Sample Sequence Input Multiplexer Select 1 (ADCSSMUX1), offset 0x060 ............... 312
Register 22: ADC Sample Sequence Input Multiplexer Select 2 (ADCSSMUX2), offset 0x080 ............... 312
Register 23: ADC Sample Sequence Control 1 (ADCSSCTL1), offset 0x064 ........................................ 313
Register 24: ADC Sample Sequence Control 2 (ADCSSCTL2), offset 0x084 ........................................ 313
Register 25: ADC Sample Sequence Input Multiplexer Select 3 (ADCSSMUX3), offset 0x0A0 ............... 315
Register 26: ADC Sample Sequence Control 3 (ADCSSCTL3), offset 0x0A4 ........................................ 316
Register 27: ADC Test Mode Loopback (ADCTMLB), offset 0x100 ....................................................... 317
Universal Asynchronous Receivers/Transmitters (UARTs) ..................................................... 318
Register 1: UART Data (UARTDR), offset 0x000 ............................................................................... 326
Register 2: UART Receive Status/Error Clear (UARTRSR/UARTECR), offset 0x004 ........................... 328
Register 3: UART Flag (UARTFR), offset 0x018 ................................................................................ 330
Register 4: UART IrDA Low-Power Register (UARTILPR), offset 0x020 ............................................. 332
Register 5: UART Integer Baud-Rate Divisor (UARTIBRD), offset 0x024 ............................................ 333
Register 6: UART Fractional Baud-Rate Divisor (UARTFBRD), offset 0x028 ....................................... 334
Register 7: UART Line Control (UARTLCRH), offset 0x02C ............................................................... 335
Register 8: UART Control (UARTCTL), offset 0x030 ......................................................................... 337
Register 9: UART Interrupt FIFO Level Select (UARTIFLS), offset 0x034 ........................................... 339
Register 10: UART Interrupt Mask (UARTIM), offset 0x038 ................................................................. 341
Register 11: UART Raw Interrupt Status (UARTRIS), offset 0x03C ...................................................... 343
Register 12: UART Masked Interrupt Status (UARTMIS), offset 0x040 ................................................. 344
Register 13: UART Interrupt Clear (UARTICR), offset 0x044 ............................................................... 345
Register 14: UART Peripheral Identification 4 (UARTPeriphID4), offset 0xFD0 ..................................... 347
Register 15: UART Peripheral Identification 5 (UARTPeriphID5), offset 0xFD4 ..................................... 348
Register 16: UART Peripheral Identification 6 (UARTPeriphID6), offset 0xFD8 ..................................... 349
Register 17: UART Peripheral Identification 7 (UARTPeriphID7), offset 0xFDC ..................................... 350
Register 18: UART Peripheral Identification 0 (UARTPeriphID0), offset 0xFE0 ...................................... 351
Register 19: UART Peripheral Identification 1 (UARTPeriphID1), offset 0xFE4 ...................................... 352
Register 20: UART Peripheral Identification 2 (UARTPeriphID2), offset 0xFE8 ...................................... 353
Register 21: UART Peripheral Identification 3 (UARTPeriphID3), offset 0xFEC ..................................... 354
Register 22: UART PrimeCell Identification 0 (UARTPCellID0), offset 0xFF0 ........................................ 355
Register 23: UART PrimeCell Identification 1 (UARTPCellID1), offset 0xFF4 ........................................ 356
Register 24: UART PrimeCell Identification 2 (UARTPCellID2), offset 0xFF8 ........................................ 357
Register 25: UART PrimeCell Identification 3 (UARTPCellID3), offset 0xFFC ........................................ 358
17April 01, 2009
Preliminary
LM3S8962 Microcontroller
Synchronous Serial Interface (SSI) ............................................................................................ 359
Register 1: SSI Control 0 (SSICR0), offset 0x000 .............................................................................. 371
Register 2: SSI Control 1 (SSICR1), offset 0x004 .............................................................................. 373
Register 3: SSI Data (SSIDR), offset 0x008 ...................................................................................... 375
Register 4: SSI Status (SSISR), offset 0x00C ................................................................................... 376
Register 5: SSI Clock Prescale (SSICPSR), offset 0x010 .................................................................. 378
Register 6: SSI Interrupt Mask (SSIIM), offset 0x014 ......................................................................... 379
Register 7: SSI Raw Interrupt Status (SSIRIS), offset 0x018 .............................................................. 381
Register 8: SSI Masked Interrupt Status (SSIMIS), offset 0x01C ........................................................ 382
Register 9: SSI Interrupt Clear (SSIICR), offset 0x020 ....................................................................... 383
Register 10: SSI Peripheral Identification 4 (SSIPeriphID4), offset 0xFD0 ............................................. 384
Register 11: SSI Peripheral Identification 5 (SSIPeriphID5), offset 0xFD4 ............................................. 385
Register 12: SSI Peripheral Identification 6 (SSIPeriphID6), offset 0xFD8 ............................................. 386
Register 13: SSI Peripheral Identification 7 (SSIPeriphID7), offset 0xFDC ............................................ 387
Register 14: SSI Peripheral Identification 0 (SSIPeriphID0), offset 0xFE0 ............................................. 388
Register 15: SSI Peripheral Identification 1 (SSIPeriphID1), offset 0xFE4 ............................................. 389
Register 16: SSI Peripheral Identification 2 (SSIPeriphID2), offset 0xFE8 ............................................. 390
Register 17: SSI Peripheral Identification 3 (SSIPeriphID3), offset 0xFEC ............................................ 391
Register 18: SSI PrimeCell Identification 0 (SSIPCellID0), offset 0xFF0 ............................................... 392
Register 19: SSI PrimeCell Identification 1 (SSIPCellID1), offset 0xFF4 ............................................... 393
Register 20: SSI PrimeCell Identification 2 (SSIPCellID2), offset 0xFF8 ............................................... 394
Register 21: SSI PrimeCell Identification 3 (SSIPCellID3), offset 0xFFC ............................................... 395
Inter-Integrated Circuit (I
2
C) Interface ........................................................................................ 396
Register 1: I
2
C Master Slave Address (I2CMSA), offset 0x000 ........................................................... 411
Register 2: I
2
C Master Control/Status (I2CMCS), offset 0x004 ........................................................... 412
Register 3: I
2
C Master Data (I2CMDR), offset 0x008 ......................................................................... 416
Register 4: I
2
C Master Timer Period (I2CMTPR), offset 0x00C ........................................................... 417
Register 5: I
2
C Master Interrupt Mask (I2CMIMR), offset 0x010 ......................................................... 418
Register 6: I
2
C Master Raw Interrupt Status (I2CMRIS), offset 0x014 ................................................. 419
Register 7: I
2
C Master Masked Interrupt Status (I2CMMIS), offset 0x018 ........................................... 420
Register 8: I
2
C Master Interrupt Clear (I2CMICR), offset 0x01C ......................................................... 421
Register 9: I
2
C Master Configuration (I2CMCR), offset 0x020 ............................................................ 422
Register 10: I
2
C Slave Own Address (I2CSOAR), offset 0x000 ............................................................ 424
Register 11: I
2
C Slave Control/Status (I2CSCSR), offset 0x004 ........................................................... 425
Register 12: I
2
C Slave Data (I2CSDR), offset 0x008 ........................................................................... 427
Register 13: I
2
C Slave Interrupt Mask (I2CSIMR), offset 0x00C ........................................................... 428
Register 14: I
2
C Slave Raw Interrupt Status (I2CSRIS), offset 0x010 ................................................... 429
Register 15: I
2
C Slave Masked Interrupt Status (I2CSMIS), offset 0x014 .............................................. 430
Register 16: I
2
C Slave Interrupt Clear (I2CSICR), offset 0x018 ............................................................ 431
Controller Area Network (CAN) Module ..................................................................................... 432
Register 1: CAN Control (CANCTL), offset 0x000 ............................................................................. 451
Register 2: CAN Status (CANSTS), offset 0x004 ............................................................................... 453
Register 3: CAN Error Counter (CANERR), offset 0x008 ................................................................... 456
Register 4: CAN Bit Timing (CANBIT), offset 0x00C .......................................................................... 457
Register 5: CAN Interrupt (CANINT), offset 0x010 ............................................................................. 459
Register 6: CAN Test (CANTST), offset 0x014 .................................................................................. 460
Register 7: CAN Baud Rate Prescaler Extension (CANBRPE), offset 0x018 ....................................... 462
April 01, 200918
Preliminary
Table of Contents
Register 8: CAN IF1 Command Request (CANIF1CRQ), offset 0x020 ................................................ 463
Register 9: CAN IF2 Command Request (CANIF2CRQ), offset 0x080 ................................................ 463
Register 10: CAN IF1 Command Mask (CANIF1CMSK), offset 0x024 .................................................. 464
Register 11: CAN IF2 Command Mask (CANIF2CMSK), offset 0x084 .................................................. 464
Register 12: CAN IF1 Mask 1 (CANIF1MSK1), offset 0x028 ................................................................ 466
Register 13: CAN IF2 Mask 1 (CANIF2MSK1), offset 0x088 ................................................................ 466
Register 14: CAN IF1 Mask 2 (CANIF1MSK2), offset 0x02C ................................................................ 467
Register 15: CAN IF2 Mask 2 (CANIF2MSK2), offset 0x08C ................................................................ 467
Register 16: CAN IF1 Arbitration 1 (CANIF1ARB1), offset 0x030 ......................................................... 468
Register 17: CAN IF2 Arbitration 1 (CANIF2ARB1), offset 0x090 ......................................................... 468
Register 18: CAN IF1 Arbitration 2 (CANIF1ARB2), offset 0x034 ......................................................... 469
Register 19: CAN IF2 Arbitration 2 (CANIF2ARB2), offset 0x094 ......................................................... 469
Register 20: CAN IF1 Message Control (CANIF1MCTL), offset 0x038 .................................................. 471
Register 21: CAN IF2 Message Control (CANIF2MCTL), offset 0x098 .................................................. 471
Register 22: CAN IF1 Data A1 (CANIF1DA1), offset 0x03C ................................................................. 473
Register 23: CAN IF1 Data A2 (CANIF1DA2), offset 0x040 ................................................................. 473
Register 24: CAN IF1 Data B1 (CANIF1DB1), offset 0x044 ................................................................. 473
Register 25: CAN IF1 Data B2 (CANIF1DB2), offset 0x048 ................................................................. 473
Register 26: CAN IF2 Data A1 (CANIF2DA1), offset 0x09C ................................................................. 473
Register 27: CAN IF2 Data A2 (CANIF2DA2), offset 0x0A0 ................................................................. 473
Register 28: CAN IF2 Data B1 (CANIF2DB1), offset 0x0A4 ................................................................. 473
Register 29: CAN IF2 Data B2 (CANIF2DB2), offset 0x0A8 ................................................................. 473
Register 30: CAN Transmission Request 1 (CANTXRQ1), offset 0x100 ................................................ 474
Register 31: CAN Transmission Request 2 (CANTXRQ2), offset 0x104 ................................................ 474
Register 32: CAN New Data 1 (CANNWDA1), offset 0x120 ................................................................. 475
Register 33: CAN New Data 2 (CANNWDA2), offset 0x124 ................................................................. 475
Register 34: CAN Message 1 Interrupt Pending (CANMSG1INT), offset 0x140 ..................................... 476
Register 35: CAN Message 2 Interrupt Pending (CANMSG2INT), offset 0x144 ..................................... 476
Register 36: CAN Message 1 Valid (CANMSG1VAL), offset 0x160 ....................................................... 477
Register 37: CAN Message 2 Valid (CANMSG2VAL), offset 0x164 ....................................................... 477
Ethernet Controller ...................................................................................................................... 478
Register 1: Ethernet MAC Raw Interrupt Status/Acknowledge (MACRIS/MACIACK), offset 0x000 ....... 489
Register 2: Ethernet MAC Interrupt Mask (MACIM), offset 0x004 ....................................................... 492
Register 3: Ethernet MAC Receive Control (MACRCTL), offset 0x008 ................................................ 493
Register 4: Ethernet MAC Transmit Control (MACTCTL), offset 0x00C ............................................... 494
Register 5: Ethernet MAC Data (MACDATA), offset 0x010 ................................................................. 495
Register 6: Ethernet MAC Individual Address 0 (MACIA0), offset 0x014 ............................................. 497
Register 7: Ethernet MAC Individual Address 1 (MACIA1), offset 0x018 ............................................. 498
Register 8: Ethernet MAC Threshold (MACTHR), offset 0x01C .......................................................... 499
Register 9: Ethernet MAC Management Control (MACMCTL), offset 0x020 ........................................ 501
Register 10: Ethernet MAC Management Divider (MACMDV), offset 0x024 .......................................... 502
Register 11: Ethernet MAC Management Transmit Data (MACMTXD), offset 0x02C ............................. 503
Register 12: Ethernet MAC Management Receive Data (MACMRXD), offset 0x030 .............................. 504
Register 13: Ethernet MAC Number of Packets (MACNP), offset 0x034 ............................................... 505
Register 14: Ethernet MAC Transmission Request (MACTR), offset 0x038 ........................................... 506
Register 15: Ethernet MAC Timer Support (MACTS), offset 0x03C ...................................................... 507
Register 16: Ethernet PHY Management Register 0 – Control (MR0), address 0x00 ............................. 508
Register 17: Ethernet PHY Management Register 1 – Status (MR1), address 0x01 .............................. 510
19April 01, 2009
Preliminary
LM3S8962 Microcontroller
Register 18: Ethernet PHY Management Register 2 – PHY Identifier 1 (MR2), address 0x02 ................. 512
Register 19: Ethernet PHY Management Register 3 – PHY Identifier 2 (MR3), address 0x03 ................. 513
Register 20: Ethernet PHY Management Register 4 – Auto-Negotiation Advertisement (MR4), address
0x04 ............................................................................................................................. 514
Register 21: Ethernet PHY Management Register 5 – Auto-Negotiation Link Partner Base Page Ability
(MR5), address 0x05 ..................................................................................................... 516
Register 22: Ethernet PHY Management Register 6 – Auto-Negotiation Expansion (MR6), address
0x06 ............................................................................................................................. 517
Register 23: Ethernet PHY Management Register 16 – Vendor-Specific (MR16), address 0x10 ............. 518
Register 24: Ethernet PHY Management Register 17 – Interrupt Control/Status (MR17), address
0x11 .............................................................................................................................. 520
Register 25: Ethernet PHY Management Register 18 – Diagnostic (MR18), address 0x12 ..................... 522
Register 26: Ethernet PHY Management Register 19 – Transceiver Control (MR19), address 0x13 ....... 523
Register 27: Ethernet PHY Management Register 23 – LED Configuration (MR23), address 0x17 ......... 524
Register 28: Ethernet PHY Management Register 24 –MDI/MDIX Control (MR24), address 0x18 .......... 525
Analog Comparator ..................................................................................................................... 526
Register 1: Analog Comparator Masked Interrupt Status (ACMIS), offset 0x000 .................................. 530
Register 2: Analog Comparator Raw Interrupt Status (ACRIS), offset 0x004 ....................................... 531
Register 3: Analog Comparator Interrupt Enable (ACINTEN), offset 0x008 ......................................... 532
Register 4: Analog Comparator Reference Voltage Control (ACREFCTL), offset 0x010 ....................... 533
Register 5: Analog Comparator Status 0 (ACSTAT0), offset 0x020 ..................................................... 534
Register 6: Analog Comparator Control 0 (ACCTL0), offset 0x024 ..................................................... 535
Pulse Width Modulator (PWM) .................................................................................................... 537
Register 1: PWM Master Control (PWMCTL), offset 0x000 ................................................................ 546
Register 2: PWM Time Base Sync (PWMSYNC), offset 0x004 ........................................................... 547
Register 3: PWM Output Enable (PWMENABLE), offset 0x008 .......................................................... 548
Register 4: PWM Output Inversion (PWMINVERT), offset 0x00C ....................................................... 549
Register 5: PWM Output Fault (PWMFAULT), offset 0x010 ................................................................ 550
Register 6: PWM Interrupt Enable (PWMINTEN), offset 0x014 ........................................................... 551
Register 7: PWM Raw Interrupt Status (PWMRIS), offset 0x018 ........................................................ 552
Register 8: PWM Interrupt Status and Clear (PWMISC), offset 0x01C ................................................ 553
Register 9: PWM Status (PWMSTATUS), offset 0x020 ...................................................................... 554
Register 10: PWM0 Control (PWM0CTL), offset 0x040 ....................................................................... 555
Register 11: PWM1 Control (PWM1CTL), offset 0x080 ....................................................................... 555
Register 12: PWM2 Control (PWM2CTL), offset 0x0C0 ...................................................................... 555
Register 13: PWM0 Interrupt and Trigger Enable (PWM0INTEN), offset 0x044 .................................... 557
Register 14: PWM1 Interrupt and Trigger Enable (PWM1INTEN), offset 0x084 .................................... 557
Register 15: PWM2 Interrupt and Trigger Enable (PWM2INTEN), offset 0x0C4 .................................... 557
Register 16: PWM0 Raw Interrupt Status (PWM0RIS), offset 0x048 .................................................... 559
Register 17: PWM1 Raw Interrupt Status (PWM1RIS), offset 0x088 .................................................... 559
Register 18: PWM2 Raw Interrupt Status (PWM2RIS), offset 0x0C8 ................................................... 559
Register 19: PWM0 Interrupt Status and Clear (PWM0ISC), offset 0x04C ........................................... 560
Register 20: PWM1 Interrupt Status and Clear (PWM1ISC), offset 0x08C ........................................... 560
Register 21: PWM2 Interrupt Status and Clear (PWM2ISC), offset 0x0CC ........................................... 560
Register 22: PWM0 Load (PWM0LOAD), offset 0x050 ....................................................................... 561
Register 23: PWM1 Load (PWM1LOAD), offset 0x090 ....................................................................... 561
Register 24: PWM2 Load (PWM2LOAD), offset 0x0D0 ....................................................................... 561
Register 25: PWM0 Counter (PWM0COUNT), offset 0x054 ................................................................ 562
April 01, 200920
Preliminary
Table of Contents
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