数据转换系统设计原理

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"Principles of Data Conversion System Design" 是一本由Behzad Razavi编著，由IEEE Press出版的专业书籍，主要关注数据转换系统的设计原理。这本书由一系列业界专家组成的编辑委员会审阅，包括John B. Anderson、R.S. Blicq、Irwin J. M. F. Moura等人，并得到了IEEE Circuits and Systems Society的支持。在数据转换系统设计这个领域，本书深入探讨了将模拟信号转换为数字信号（ADC，模拟到数字转换器）和数字信号转换为模拟信号（DAC，数字到模拟转换器）的基本理论与实践方法。这些转换过程在现代电子设备中至关重要，例如通信系统、信号处理和图像显示等领域。内容可能涵盖了以下关键知识点： 1. **转换器架构**：介绍不同类型的ADC和DAC架构，如逐次逼近、积分型、双极型、Σ-Δ调制等，以及它们各自的优势和限制。 2. **噪声和精度**：讨论数据转换过程中引入的噪声源，如何衡量转换精度（如ENOB，有效位数），以及如何优化系统以提高信噪比。 3. **线性度和失真**：分析转换器的非线性效应，如量化误差、失调、增益误差和谐波失真，以及如何通过校准和补偿技术来减少它们。 4. **速度与功耗**：探讨高速转换器的设计挑战，包括功耗与速度之间的权衡，以及如何在低功耗条件下实现高速转换。 5. **时序与同步**：讲解采样定理的应用，时钟同步的重要性，以及如何处理时钟偏移和抖动对转换结果的影响。 6. **数字接口**：讨论数据转换器与数字系统的接口设计，包括串行和并行接口，以及高速接口标准如LVDS（低压差分信号）。 7. **系统级设计**：介绍如何在系统层面集成ADC和DAC，考虑整个信号链路的性能，包括前端放大器、滤波器和抗混叠技术。 8. **应用实例**：提供实际案例，如无线通信中的OFDM（正交频分复用）系统、医疗成像设备或音频系统中数据转换器的使用。 9. **设计工具和仿真**：讨论用于设计和验证数据转换系统的工具，如SPICE模拟和MATLAB仿真。 10. **测试与评估**：介绍如何测试和评估数据转换器的性能，包括标准测试信号和评估板的使用。通过深入学习这本书，读者可以掌握数据转换系统设计的关键概念和技术，从而能够设计出高效、高精度的数据转换解决方案。

Basic Sampling Circuits Chap.

range can be extended to supply rails if the switch is realized as a comple

mentary pair. As depicted in Figure 2.10, this is accomplished by controlling

the gates of an NMOS and a PMOS device with complementary clocks so

that the two devices

turn

on and off simultaneously. In this circuit, the NMOS

transistor conducts for

Vi,

VDD

VT~~,

while the PMOS device is

on for

VTwl

Vjn

VDD,

thereby providing a rail

rail input and output

range.

Fig.

2.10

Complementary

MOS

sampling switches.

addition to an extended range, the circuit of Figure 2.10 has another

important advantage over that of Figure

2.5:

the equivalent on

resistance of

a CMOS switch, compared with that of a single NMOS or PMOS device,

varies much less as a function of the input voltage. Figure 2.11 plots the

on-

resistance of an NMOS, a PMOS, and a complementary MOS switch versus

the input voltage, indicating only a small peak in the CMOS on

resistance

near the middle of the range. The relatively constant on

resistance across the

entire

input/output range allows reasonable sizes for the switches and also

minimizes the harmonic distortion caused by variation of switch resistance.

While it may seem that

and

Figure 2.10 cancel each other's

charge injection if they have identical dimensions, equation (2.1 1) indicates

that

QCh

depends on

VGS

VTH

(

and hence will not be equal for

and

has an arbitrary value.

In high

speed applications, the complementary clocks

required

for

CMOS switches can pose timing problems. Unless the clockedges are aligned

such that the two transistors

turn

off at precisely the same instant, either one

could be conducting weakly for a short while, introducing an input

dependent

phase shift or sampling instant.

important feature of MOS switches is that they introduce zero offset

(level shift) from their source to their drain if the following circuit draws

Sec.

2.3

Sampling Switches

Fig.

2.11

Variation @on-resistance of

NMOS,

PMOS,

and CMOS switches.

current. This is in contrast with the behavior of diode switches described

below.

2.3.2

Diode

Switches

Semiconductor diodes exhibit small on

resistance, large off

resistance,

high

speed switching, and thus potential for the switching function in sam

pling circuits.

simplified diagram of a typical diode switch is shown in Fig

ure 2.12

[8].

Here, four diodes form

bridge that provides a low

impedance

path from

Vout

when current sources

and

are on and (in the ideal

case) isolates

VOut

from

when

and

are off. Nominally,

For small signals at

X,,

and

Vout,

the equivalent on

resistance of the

switch,

Ron,

is equal to the parallel combination of the resistance of the two,

branches consisting of

and

D3-

Dq.

Each diode exhibits an incremental

resistance,

l/gm, resulting from its exponential

characteristics, as well

as an ohmic

resistance,'rd, due to contact and material resistance. Thus,

rd.

order to minimize

Ron,

can be increased by raising the bias current

can be lowered by increasing the area of each diode. The latter remedy,

however, increases the junction capacitance of thediodes, thus causing larger

feedthrough

the hold mode. This effect is quantified later.

Actual implementations of the diode sampling bridge often control only

one

of the current sources, usually

12,

while the other is always on. This

is because it is difficult to

turn

off

and

at precisely the same instant,

Basic Sampling Circuits Chap.

Fig.

2.12

Diode sampling switch.

especially if high

speed pnp or PMOS transistors are not available. Figure

2.13(a) illustrates such an implementation. Here, when

is high, Q

off,

Q2 is on, and the circuit is in the acquisition mode. When

goes low,

turns on, Q2 and hence the bridge

turn

off, and the circuit enters the hold

mode. Note that

need not be a high

speed device for it operates as a passive

component, but the capacitance it introduces at node

is critical.

In the circuit of Figure

2.13(a), when

is low and the bridge is off, Q

may enter saturation because the voltage at node

is not well

defined. Figure

2.13(b) depicts a modification where clamp diodes Dg and D6 and current

source

are added to the circuit. Qpically,

and the clamp

voltage

is at the midpoint of the input voltage range. When

is high,

Q2 sinks both

and

13,

and

are reverse

biased

(on)

Vi,

VBl

VD3(on).

When

goes low,

flows from node

Ds turns

on, and

is clamped to

VBl

VDS(on),

while

flows through

and

clamped to

VD6(on).

The variation of the on

resistance of a diode switch as a function of the

input voltage is different from that of a MOS device.

the circuit of Figure

2.13, when the input voltage goes through a positive excursion,

draws

current from

Dz; therefore, Dl and D4 conduct less, whereas D2 and D3

conduct more. If the change in the currents of

D1-D4 is a small fraction of

their quiescent current

ID,

then the increase in the resistance of Dl and

is compensated by the decrease in the resistance of D2 and D3, respectively,

Sec.

2.3

"1"

Sampling Switches

Fig.

2.13

(a) Simple bipolar sampling bridge; (b) modifiedcircuit with clamp

diodes.

thereby yielding negligible variation in the on

resistance of the overall switch.

We can formulate the above condition by noting that if

Vin

Vout

sin

wt,

(2.16)

then the maximum current drawn by

occurs when

nnlw

and is equal to

V0"t

Imax

Ir=nn/a~

(2.17)

This current must remain much less than

i.e.,

The charge injection and feedthrough behavior of diode switches is also

different from that of MOS devices. Since a diode biased at a current

carries a charge equal to

t~,

where

is the transit time, the charge

injection error is relatively constant because, as explained above, in a properly

designed switch

remains fairly constant. Thus, charge injection introduces

only a constant offset in the

inputloutput characteristic. On the other hand,

Basic Sampling Circuits Chap.

in the diode bridge of Figure 2.13(b) the change in Vx and Vy, which is

coupled to the output through the junction capacitance of

and

D4,

causes

nonlinearity and gain error

[9].

To understand why, note that in the tracking

mode,

Vin

V~(on) and Vy

fin

VD(on), whereas

the hold mode,

VD(on) and VY

VD(on). Consequently,

the transition

from tracking to hold,

Vx drops by

fin

VBI

2VD(on) and Vy rises by

VBI

Vi,

2V~(on), creating an input

dependent pedestal at VOut. Since the

junction capacitance of

and

is voltage

dependent, the pedestal

has

significant nonlinear component.

In order to eliminate the input dependence of the pedestal,

VBl can

be bootstrapped to the held output voltage

[9].

This is illustrated in Figure

2.14, where the unity

gain buffer

provides a clamp voltage equal to the

held level. Now

Vx and Vy change by -2VD(on) and +2VD(,,), respectively,

yielding substantially less nonlinearity.

"cc

Fig.

2.14

Sampling

bridge with bootstrapped clamp voltage.

The hold

mode feedthrough of sampling bridges depends on the junction

capacitance of the bridge diodes and the on

resistance of the clamp devices.

Sec.

2.3

Sampling Switches

For example, when the circuit of Figure 2.13(b) is in the hold mode,

can

be simplified

shown in Figure

2.15,

where the junction capacitance

is modeled with Cj, and the on

resistance of

and

D,j

with Ron. For

CH,

the feedthrough transfer function is expressed as

Fig.

2.15

Simplified circuit of diode bridge

the

hold mode.

important drawback of diode switches is the limitation they impose

the input and output voltage swings.

the circuit of Figure 2.13(a),

t sources

and

typically require at least

0.5

to maintain a high

impedance, the bridge consumes

2VD(on)

1.6

of the headroom,

of approximately

0.5

to operate in the forward

t, the maximum voltage swing at

and VOut

drawback of diode switches is the dc offset from input to output

device mismatches. For example, if in Figure

2.13(a),

IC2

and

are mismatched, then the output offset voltage is

where

AIs/Is

is the relative mismatch between the saturation currents of

and

D4.

2.3.3

Comparison

MOS and Diode Switches

Following our study of

MOS

and diode switches in the last two sections,

an now compare their properties.

Diode switches generally have a lower on

resistance than

MOS

switches. If each diode in a bridge is biased at

0.5

rnA

and has a

Basic Sampling

Circuits

Chap.

series (ohmic) resistance of 40

then the equivalent on

resistance

of the bridge is approximately 90

52.

Attaining such a low resistance

with a

MOSFET

usually requires very large width

length ratios,

typically greater than 1000. This

turn exacerbates charge injection

and clock feedthrough problems.

The on

resistance and charge injection of diode switches depend much

less on the input voltage than do those of

MOS

devices, making the

former more attractive for high

precision open

loop applications.

Diode switches such as that of Figure 2.13 operate with clock voltage

swings roughly an order of magnitude smaller than those of

MOS

cir

cuits, allowing sharper edges and better definition of sampling points

time. For this reason and because of lower noise

ECL

circuits

than in

MOS

circuits, diode switches have a potentially lower jitter

than their

MOS

counterparts.

The input voltage range of

MOS

sampling circuits is generally larger

than that of diode switches, thus allowing a wider dynamic range.

MOS

switches introduce no dc level shift (offset) from the input to

the output if the following circuit draws no current. Diode bridges,

on the other hand, suffer from a finite offset caused by mismatches in

current sources and diodes.

Diode switches are typically much more complex and dissipate much

more power than

MOS

sampling circuits. The circuit of Figure

2.13(b), for example, requires at least six diodes, a differential pair,

and three current sources whose magnitudes and variations with tem

perature and process must be well

controlled.

MOS

sampling

switch, on the other hand, consists of one or two transistors. While

this difference in complexity and power dissipation may not be sig

nificant for a single SHA, it becomes important if a sampled

data

system such as an

A/D

converter or a filter requires a great number

of sampling switches.

2.3.4

Improvements in

MOS

Switch Performance

The simplicity of

MOS

switches has made them attractive for large

scale

analog integrated circuits. However, as discussed in previous sections,

MOS

devices suffer from large on

resistance and substantial charge stored in their

channel. In fact, the strong trade

off between these two parameters limits the

level of speed

accuracy that can be achieved in a simple circuit such as that

of Figure

2.5.

We can formulate this trade

off by defining a figure of merit:

[fpedestal error)

(acquisition time)]-'

(2.22)

Sec.

2.3

Sampling

Switches

The pedestal error is

Qch

AV,

~CH

where we have assumed half of the channel charge of the switch is injected

onto

and neglected clock feedthrough. The acquisition time constant is

Note that since

taCq

depends on the gate

source voltage and hence varies with

input, modeling the acquisition behavior with a single time constant is only a

rough approximation.

From (2.24) and

(2.26), it follows that

This equation indicates that, in a given

CMOS

technology, the

MOS

sampling

circuit of Figure 2.5 does not achieve

speed

accuracy product higher than

roughly

~/.L,/L~.

This product is further degraded by clock feedthrough.

In order to relax the trade

off given by (2.28), a number of circuit tech

niques have been proposed, two of which are illustrated in Figure 2.16. In

Figure

2.16(a), a dummy device

with half the width of the sampling switch

(and the same length) is added and driven by

the complement of the

sampling clock

[lo]. In this circuit, when

turns off and injects charge

onto

CH,

turns on and absorbs charge from

in its channel.

Thus,

if exactly half of the

channel charge is injected onto

CH,

then complete

cancellation occurs and the held voltage on

is not corrupted by the charge

injection. However, the fraction of channel charge injected by

onto its

source and drain depends on the impedance seen at the input and output nodes

and the clock transition speed

[6], indicating that

may not receive half

of the

channel charge and that this scheme may not provide accurate

cancellation.

Figure

2.16(b) shows another sampling configuration, where the circuit

is implemented in differential form

[l 11.

this topology,

Vin,

and

Vin,2

are differential inputs (i.e., they vary by the same amount but in opposite

Basic Sampling

Circuits Chap.

Fig.

2.16

Cancellation of

MOS

charge injection using (a) a dummy switch

and

(b)

differential operation.

directions) and

Vo,t,l

and

Vout,2

are differential outputs (i.e., their difference

is sensed by the following circuit). Charge injection and clock feedthrough

errors at

V,,ut,l

and

Vout,2

are to the first order equal and hence appear as a

common-mode (CM) component at the output.

important error, however,

still exists here: since the channel charge of

and

is a function of

their

VcjS

and since fin,,

Lv2,

the differential held output includes an

input

dependent charge injection error

term.

This

term

introduces gain error

and nonlinearity, limiting the usefulness of this topology only to applications

where

Vi,

vnoz

is much less

than

the

VGS

VTH

of the switches.

Another MOS sampling technique is depicted in Figure

2.17.

the

acquisition mode,

and

are on,

is off,

Vout

VDD,

and the capacitor

voltage tracks the input. In the transition to the hold mode, first

goes low,

turning off

M2,

and after a small delay

falls, turning

off and

on.

Thus,

drops from

Vi,

and hence the change in

VOut

is equal to

-Vi,

at the sampling instant. Since

always turns off first, the channel charge

MI-which is input

dependent

does not introduce any error. Moreover,

as the gate

source voltage of

is independent of

Vi,,

the channel charge

injected by this switch appears as a constant offset at the output.

While suppressing input-dependent charge injection, the circuit of Fig

ure 2.17 suffers from another source of nonlinearity that limits its speed. In

the transition to hold, when

Vout

falls from

VDD

VDo

Vin, a voltage di

vision occurs between CH and the drain junction capacitance of

M2,

yielding

nonlinear component in

Vout.

Since this capacitance is proportional to the

device width, it trades directly with the on-resistance and hence the acqui-

sition time. Nevertheless, differential versions of this topology can provide

relatively high speed and high linearity.

Chap.

References

Fig.

2.17

CMOS

sampling circuit with series capacitor.

Appendix

Effect

ofAperttcre Jitter on

SNR

Consider

sine wave

sin

2rrfint sampled at t

kTs

where

is the aperture jitter.

Since

eacb sampling instant can deviate from its ideal value by

the sampled

amplitude has an error of rdV.,/dt. Thus, the overall sampled waveform

can be viewed as the sum of an ideal sine wave and a noise component.

calculate the SNR for an otherwise ideal sampling circuit, we assume that

is a random process uncorrelated with

and express the noise power as

where

?(=

rk)

denotes the mean squared value

[12].

Thus,

SNR

10g(2~rfi~.,,) dB.

(2.3

"his

relation proves useful

jitter is the dominant source of noise in a system.

In a general case, other sources of noise must

taken into account as well.

REFERENCES

[I]

Gregorian and G. C. Temes, Analog

MOS

Integrated Circuits for

Signal Processing, John Wiley and Sons, New York, 1986.

(21

Rush and D.

Oldfield,

Data Acquisition System for a 1-GHz

Digitizing Oscilloscope,

Hewlett-Packard

J.,

April 1986, pp. 4

[3]

Tewksbury, et al..

Tenninology Related to the Performance of

S/H,

AID,

and DIA Circuits,

IEEE

Trans. Circuits Syst., vol. CAS

25,

pp.

419-426,

July

1978.

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