xx List of Figures
Fig. 5.4 LED and sampling pulse structure for conventional (uniform
sampling) and CS PPG acquisition .................................. 73
Fig. 5.5 The architecture of a single channel CS PPG acquisition
ASIC which embeds a DBE for feature extraction ................. 74
Fig. 5.6 Ideal PD and TIA interface. The TIA is formed by
employing resistive feedback around an OTA ...................... 75
Fig. 5.7 (a) Ideal PD and (b) a practical PD with shunt resistance
(R
p
) and reverse bias junction capacitance (C
p
) ................... 75
Fig. 5.8 (a) Equivalent circuit for loop gain computation of TIA. (b)
Equivalent circuit for return ratio computation ..................... 76
Fig. 5.9 Magnitude response of A
OL
and the reciprocal of feedback
fraction
1
β
.......................................................... 77
Fig. 5.10 Lead-lag compensated TIA. Stability margin is enhanced by
inserting a feedback capacitor (C
f
) into the network, which
introduces a left half plane (LHP) zero ............................. 77
Fig. 5.11 (a) Equivalent circuit for loop gain computation of the
lead-lag compensated TIA. (b) Equivalent circuit for return
ratio computation .................................................... 78
Fig. 5.12 Measured reverse bias junction capacitance of the
photodiode used in the current work as a function of reverse
bias voltage ........................................................... 79
Fig. 5.13 TIA interfaced with a current DAC (IDAC) at the input.
IDAC enables active rejection of I
dc
, relaxing the channel
DR requirements ..................................................... 80
Fig. 5.14 Schematic of the 5-bit current DAC (IDAC) used to subtract
static component of photocurrent ................................... 80
Fig. 5.15 Two stage Miller compensated OTA with resistive source
degenerated current source in the first stage. This OTA core
is used to realize the TIA and SI .................................... 81
Fig. 5.16 Switched integrator (SI) implementation in the current
work. The output of the TIA is further amplified and filtered
through SI ............................................................ 82
Fig. 5.17 Switched integrator (SI) as noise limiting filter in the PPG
readout channel ....................................................... 83
Fig. 5.18 Schematic of the 12-bit SAR ADC with a unit capacitor of
800 fF ................................................................. 84
Fig. 5.19 The simplified architecture of the digital back end (DBE) ......... 85
Fig. 5.20 Key timing signals for AFE and LED driver control ............... 86
Fig. 5.21 Eight-way multiply accumulate (MAC) unit for accelerating
PSD estimation ....................................................... 87
Fig. 5.22 Chip micrograph of the CS PPG ASIC ............................. 88
Fig. 5.23 (Top) Measured output of the channel for a DC current
excitation of LED in uniform sampling mode. (Bottom)
Zoomed in view of response during one sampling instant ......... 89