Intel
®
82599 10 GbE Controller—Contents
18 331520-005
11.6.2 EEPROM....................................................................................................................945
12.0 Design Considerations and Guidelines ...................................................................947
12.1 Connecting the PCIe Interface .................................................................................................... 947
12.1.1 Link Width Configuration ............................................................................................. 947
12.1.2 Polarity Inversion and Lane Reversal............................................................................. 948
12.1.3 PCIe Reference Clock.................................................................................................. 948
12.1.4 PCIe Analog Bias Resistor............................................................................................ 948
12.1.5 Miscellaneous PCIe Signals .......................................................................................... 948
12.1.6 PCIe Layout Recommendations .................................................................................... 948
12.2 Connecting the MAUI Interfaces ................................................................................................. 949
12.2.1 MAUI Channels Lane Connections ................................................................................. 949
12.2.2 MAUI Bias Resistor ..................................................................................................... 949
12.2.3 XAUI, KX/KR, BX4, CX4, BX and SFI+ Layout Recommendations ...................................... 949
12.2.4 Board Stack-Up Example............................................................................................. 950
12.2.5 Trace Geometries....................................................................................................... 950
12.2.6 Other High-Speed Signal Routing Practices .................................................................... 951
12.2.7 Reference Planes........................................................................................................ 954
12.2.8 Dielectric Weave Compensation.................................................................................... 956
12.2.9 Impedance Discontinuities........................................................................................... 957
12.2.10 Reducing Circuit Inductance......................................................................................... 957
12.2.11 Signal Isolation.......................................................................................................... 958
12.2.12 Power and Ground Planes............................................................................................ 958
12.2.13 KR and SFI+ Recommended Simulations ....................................................................... 964
12.2.14 Additional Differential Trace Layout Guidelines for SFI+ Boards ........................................ 965
12.3 Connecting the Serial EEPROM ................................................................................................... 967
12.3.1 Supported EEPROM Devices......................................................................................... 967
12.4 Connecting the Flash ................................................................................................................ 967
12.4.1 Supported Flash Devices ............................................................................................. 968
12.5 SMBus and NC-SI ..................................................................................................................... 968
12.6 NC-SI ..................................................................................................................................... 970
12.6.1 NC-SI Design Requirements......................................................................................... 970
12.6.2 NC-SI Layout Requirements......................................................................................... 972
12.7 Resets .................................................................................................................................... 977
12.8 Connecting the MDIO Interfaces ................................................................................................. 978
12.9 Connecting the Software-Definable Pins (SDPs) ............................................................................ 978
12.10 Connecting the Light Emitting Diodes (LEDs) ................................................................................ 978
12.11 Connecting Miscellaneous Signals ............................................................................................... 979
12.11.1 LAN Disable............................................................................................................... 979
12.11.2 BIOS Handling of Device Disable .................................................................................. 980
12.12 Oscillator Design Considerations ................................................................................................. 980
12.12.1 Oscillator Types .........................................................................................................981
12.12.2 Oscillator Solution ......................................................................................................981
12.12.3 Oscillator Layout Recommendations.............................................................................. 982
12.12.4 Reference Clock Measurement Recommendations ........................................................... 982
12.13 Power Supplies ........................................................................................................................ 982
12.13.1 Power Supply Sequencing............................................................................................ 982
12.13.2 Power Supply Filtering ................................................................................................ 983
12.13.3 Support for Power Management and Wake Up ................................................................ 983
12.14 Connecting the JTAG Port .......................................................................................................... 984
13.0 Thermal Design Recommendations .......................................................................985