Intel 82599 10 GbE 控制器技术规格详解

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"Intel 82599 10 GbE Controller 是一款由Intel公司推出的高性能以太网控制器，主要特点包括双端口10 Gigabit Ethernet（10GbE）设备或单端口配置（82599EN），支持多种网络标准，并提供了丰富的硬件加速功能。该控制器的数据手册详细介绍了其寄存器、EEprom接口和其他关键特性，是了解和使用该芯片的重要参考资料。" Intel 82599 10 GbE Controller是一款针对高速网络通信设计的控制器，其主要特性包括： 1. **双端口或单端口配置**：该控制器可以作为双端口10GbE设备使用，提供高带宽连接，同时也有单端口版本（82599EN）供选择。 2. **存储接口**：具备Serial Flash Interface和4-wire SPI EEPROM接口，用于存储和读取配置信息，其中EEPROM空间还可以进行保护，用于私有配置。 3. **LED操作定制**：允许软件或OEM厂商自定义LED显示，以适应不同的应用场景。 4. **设备禁用功能**：提供设备禁用选项，可根据需求关闭控制器功能。 5. **封装尺寸**：控制器的封装尺寸为25mm x 25mm，适合紧凑型设计。在网络功能方面，82599 10 GbE Controller遵循以下标准： 1. **网络标准兼容性**：符合10Gb/s和1Gb/s Ethernet / 802.3ap（KX / KX4 / KR）规范，以及10Gb/s Ethernet / 802.3ae（XAUI）规范，同时也支持1000BASE-BX和IEEE 802.3x 100BASE-TX标准。 2. **大帧支持**：支持最大15.5KB的Jumbo帧，提高数据传输效率。 3. **自动协商**：采用 Clause 73 自动协商，可自动适应不同的网络速度和双工模式。 4. **CX4接口**：根据802.3ak标准提供CX4连接，适用于高速环境。 5. **流量控制**：支持发送和接收暂停帧，以及接收FIFO阈值，确保网络稳定。 6. **管理与监控**：提供统计信息，支持RMON（远程网络监控），方便网络管理和故障排查。 7. **VLAN支持**：符合802.1q VLAN标准，可实现虚拟局域网划分。 8. **硬件加速**：支持TCP分段卸载，最大可达256KB，减轻CPU负担；同时支持IPv6，包括IP/TCP和IP/UDP接收校验和卸载；还提供了分片UDP校验和卸载功能，用于包重组，进一步优化性能。综上，Intel 82599 10 GbE Controller是面向高端网络应用的高性能解决方案，它通过硬件加速和各种网络协议的支持，确保了高效、可靠的数据传输，并为系统集成提供了高度的灵活性和定制化能力。

Intel

82599 10 GbE Controller—Contents

16 331520-005

7.11.6 RSC Completion and Aging .......................................................................................... 472

7.12 IPsec Support .......................................................................................................................... 474

7.12.1 Overview ..................................................................................................................474

7.12.2 Hardware Features List ............................................................................................... 474

7.12.3 Software/Hardware Demarcation.................................................................................. 477

7.12.4 IPsec Formats Exchanged Between Hardware and Software ............................................. 478

7.12.5 Tx SA Table...............................................................................................................482

7.12.6 Tx Hardware Flow ...................................................................................................... 483

7.12.7 AES-128 Operation in Tx ............................................................................................. 485

7.12.8 Rx Descriptors ...........................................................................................................487

7.12.9 Rx SA Tables ............................................................................................................. 487

7.12.10 Rx Hardware Flow without TCP/UDP Checksum Offload.................................................... 490

7.12.11 Rx Hardware Flow with TCP/UDP Checksum Offload ........................................................ 491

7.12.12 AES-128 Operation in Rx............................................................................................. 491

7.13 Fibre Channel over Ethernet (FCoE) ............................................................................................ 493

7.13.1 Introduction ..............................................................................................................493

7.13.2 FCoE Transmit Operation............................................................................................. 494

7.13.3 FCoE Receive Operation .............................................................................................. 500

7.14 Reliability ................................................................................................................................ 516

7.14.1 Memory Integrity Protection ........................................................................................ 516

7.14.2 PCIe Error Handling.................................................................................................... 516

8.0 Programming Interface .........................................................................................517

8.1 Address Regions ....................................................................................................................... 517

8.1.1 Memory-Mapped Access .............................................................................................. 517

8.1.2 I/O-Mapped Access..................................................................................................... 518

8.1.3 Registers Terminology ................................................................................................ 520

8.2 Device Registers — PF ............................................................................................................... 521

8.2.1 MSI-X BAR Register Summary PF ................................................................................. 521

8.2.2 Registers Summary PF — BAR 0................................................................................... 521

8.2.3 Detailed Register Descriptions — PF.............................................................................. 541

8.3 Device Registers — VF .............................................................................................................. 732

8.3.1 Registers Allocated Per Queue...................................................................................... 732

8.3.2 Non-Queue Registers.................................................................................................. 732

8.3.3 MSI—X Register Summary VF — BAR 3 ......................................................................... 733

8.3.4 Registers Summary VF — BAR 0................................................................................... 735

8.3.5 Detailed Register Descriptions —VF............................................................................... 737

9.0 PCIe Programming Interface ................................................................................747

9.1 PCI Compatibility ...................................................................................................................... 747

9.2 Configuration Sharing Among PCI Functions ................................................................................. 748

9.3 PCIe Register Map .................................................................................................................... 750

9.3.1 Register Attributes ..................................................................................................... 750

9.3.2 PCIe Configuration Space Summary.............................................................................. 750

9.3.3 Mandatory PCI Configuration Registers — Except BARs.................................................... 752

9.3.4 Subsystem ID Register (0x2E; RO) ............................................................................... 755

9.3.5 Cap_Ptr Register (0x34; RO) ....................................................................................... 755

9.3.6 Mandatory PCI Configuration Registers — BARs.............................................................. 756

9.3.7 PCIe Capabilities ........................................................................................................ 757

9.3.8 MSI-X Capability ........................................................................................................ 763

9.3.9 VPD Registers............................................................................................................ 768

9.3.10 PCIe Configuration Registers........................................................................................ 769

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Contents—Intel

82599 10 GbE Controller

9.4 PCIe Extended Configuration Space ............................................................................................. 780

9.4.1 Advanced Error Reporting Capability (AER) .................................................................... 781

9.4.2 Serial Number............................................................................................................ 786

9.4.3 Alternate Routing ID Interpretation (ARI) Capability Structure.......................................... 788

9.4.4 IOV Capability Structure.............................................................................................. 789

9.5 Virtual Functions Configuration Space .......................................................................................... 796

9.5.1 Mandatory Configuration Space ....................................................................................798

9.5.2 PCI Capabilities..........................................................................................................800

10.0 Manageability .......................................................................................................803

10.1 Platform Configurations ............................................................................................................. 803

10.1.1 On-Board BMC Configurations ...................................................................................... 803

10.1.2 82599 NIC.................................................................................................................804

10.2 Pass-Through (PT) Functionality ................................................................................................. 804

10.2.1 DMTF NC-SI Mode ......................................................................................................805

10.2.2 SMBus Pass-Through (PT) Functionality.........................................................................807

10.3 Manageability Receive Filtering ................................................................................................... 811

10.3.1 Overview and General Structure...................................................................................811

10.3.2 L2 EtherType Filters.................................................................................................... 813

10.3.3 VLAN Filters - Single and Double VLAN Cases ................................................................. 813

10.3.4 L3 and L4 Filters ........................................................................................................814

10.3.5 Manageability Decision Filters ...................................................................................... 816

10.3.6 Possible Configurations ...............................................................................................818

10.4 LinkSec and Manageability ......................................................................................................... 820

10.4.1 Handover of LinkSec Responsibility Between BMC and Host.............................................. 821

10.5 Manageability Programming Interfaces ........................................................................................ 824

10.5.1 NC-SI Programming....................................................................................................824

10.5.2 SMBus Programming................................................................................................... 873

10.5.3 Manageability Host Interface........................................................................................ 910

10.5.4 Software and Firmware Synchronization ........................................................................ 914

11.0 Electrical/Mechanical Specification .......................................................................917

11.1 Introduction .............................................................................................................................917

11.2 Operating Conditions ................................................................................................................ 917

11.2.1 Absolute Maximum Ratings .......................................................................................... 917

11.2.2 Recommended Operating Conditions ............................................................................. 918

11.3 Power Delivery ......................................................................................................................... 918

11.3.1 Power Supply Specifications......................................................................................... 918

11.3.2 In-Rush Current ......................................................................................................... 920

11.4 DC/AC Specification .................................................................................................................. 920

11.4.1 DC Specifications .......................................................................................................920

11.4.2 Digital I/F AC Specifications ......................................................................................... 925

11.4.3 PCIe Interface AC/DC Specification ...............................................................................936

11.4.4 Network (MAUI) Interface AC/DC Specification ............................................................... 937

11.4.5 SerDes Crystal/Reference Clock Specification ................................................................. 938

11.5 Package .................................................................................................................................. 943

11.5.1 Mechanical ................................................................................................................943

11.5.2 Thermal ....................................................................................................................943

11.5.3 Electrical ................................................................................................................... 943

11.5.4 Mechanical Package .................................................................................................... 944

11.6 Devices Supported .................................................................................................................... 944

11.6.1 Flash ........................................................................................................................ 944

Intel

82599 10 GbE Controller—Contents

18 331520-005

11.6.2 EEPROM....................................................................................................................945

12.0 Design Considerations and Guidelines ...................................................................947

12.1 Connecting the PCIe Interface .................................................................................................... 947

12.1.1 Link Width Configuration ............................................................................................. 947

12.1.2 Polarity Inversion and Lane Reversal............................................................................. 948

12.1.3 PCIe Reference Clock.................................................................................................. 948

12.1.4 PCIe Analog Bias Resistor............................................................................................ 948

12.1.5 Miscellaneous PCIe Signals .......................................................................................... 948

12.1.6 PCIe Layout Recommendations .................................................................................... 948

12.2 Connecting the MAUI Interfaces ................................................................................................. 949

12.2.1 MAUI Channels Lane Connections ................................................................................. 949

12.2.2 MAUI Bias Resistor ..................................................................................................... 949

12.2.3 XAUI, KX/KR, BX4, CX4, BX and SFI+ Layout Recommendations ...................................... 949

12.2.4 Board Stack-Up Example............................................................................................. 950

12.2.5 Trace Geometries....................................................................................................... 950

12.2.6 Other High-Speed Signal Routing Practices .................................................................... 951

12.2.7 Reference Planes........................................................................................................ 954

12.2.8 Dielectric Weave Compensation.................................................................................... 956

12.2.9 Impedance Discontinuities........................................................................................... 957

12.2.10 Reducing Circuit Inductance......................................................................................... 957

12.2.11 Signal Isolation.......................................................................................................... 958

12.2.12 Power and Ground Planes............................................................................................ 958

12.2.13 KR and SFI+ Recommended Simulations ....................................................................... 964

12.2.14 Additional Differential Trace Layout Guidelines for SFI+ Boards ........................................ 965

12.3 Connecting the Serial EEPROM ................................................................................................... 967

12.3.1 Supported EEPROM Devices......................................................................................... 967

12.4 Connecting the Flash ................................................................................................................ 967

12.4.1 Supported Flash Devices ............................................................................................. 968

12.5 SMBus and NC-SI ..................................................................................................................... 968

12.6 NC-SI ..................................................................................................................................... 970

12.6.1 NC-SI Design Requirements......................................................................................... 970

12.6.2 NC-SI Layout Requirements......................................................................................... 972

12.7 Resets .................................................................................................................................... 977

12.8 Connecting the MDIO Interfaces ................................................................................................. 978

12.9 Connecting the Software-Definable Pins (SDPs) ............................................................................ 978

12.10 Connecting the Light Emitting Diodes (LEDs) ................................................................................ 978

12.11 Connecting Miscellaneous Signals ............................................................................................... 979

12.11.1 LAN Disable............................................................................................................... 979

12.11.2 BIOS Handling of Device Disable .................................................................................. 980

12.12 Oscillator Design Considerations ................................................................................................. 980

12.12.1 Oscillator Types .........................................................................................................981

12.12.2 Oscillator Solution ......................................................................................................981

12.12.3 Oscillator Layout Recommendations.............................................................................. 982

12.12.4 Reference Clock Measurement Recommendations ........................................................... 982

12.13 Power Supplies ........................................................................................................................ 982

12.13.1 Power Supply Sequencing............................................................................................ 982

12.13.2 Power Supply Filtering ................................................................................................ 983

12.13.3 Support for Power Management and Wake Up ................................................................ 983

12.14 Connecting the JTAG Port .......................................................................................................... 984

13.0 Thermal Design Recommendations .......................................................................985

331520-005 19

Contents—Intel

82599 10 GbE Controller

13.1 Thermal Considerations .............................................................................................................985

13.2 Importance of Thermal Management ...........................................................................................986

13.3 Packaging Terminology .............................................................................................................. 986

13.4 Thermal Specifications .............................................................................................................. 987

13.5 Case Temperature .................................................................................................................... 988

13.6 Thermal Attributes .................................................................................................................... 988

13.6.1 Designing for Thermal Performance .............................................................................. 988

13.6.2 Model System Definition..............................................................................................988

13.6.3 Package Thermal Characteristics .................................................................................. 989

13.7 Thermal Enhancements ............................................................................................................. 990

13.8 Clearances ............................................................................................................................... 990

13.9 Default Enhanced Thermal Solution ............................................................................................. 992

13.10 Extruded Heatsinks ................................................................................................................... 993

13.11 Attaching the Extruded Heatsink .................................................................................................994

13.11.1 Clips......................................................................................................................... 994

13.11.2 Thermal Interface (PCM45 Series) ................................................................................ 994

13.11.3 Avoid Damaging Die-Side Capacitors with Heat Sink Attached ..........................................994

13.11.4 Maximum Static Normal Load....................................................................................... 995

13.12 Reliability ................................................................................................................................ 996

13.12.1 Thermal Interface Management for Heatsink Solutions .................................................... 996

13.13 Measurements for Thermal Specifications .................................................................................... 997

13.13.1 Case Temperature Measurements................................................................................. 997

13.13.2 Attaching the Thermocouple (No Heatsink) .................................................................... 998

13.13.3 Attaching the Thermocouple (Heatsink) ......................................................................... 998

13.14 Heatsink and Attach Suppliers .................................................................................................... 999

13.15 PCB Guidelines ....................................................................................................................... 1000

14.0 Diagnostics ......................................................................................................... 1001

14.1 Link Loopback Operations ........................................................................................................ 1001

15.0 Glossary and Acronyms ....................................................................................... 1003

15.1 Register Attributes .................................................................................................................. 1014

Appendix A Packets and Frames................................................................................ 1015

A.1 Legacy Packet Formats ............................................................................................................ 1015

A.1.1 ARP Packet Formats ................................................................................................. 1015

A.1.2 IP and TCP/UDP Headers for TSO ............................................................................... 1017

A.1.3 Magic Packet ........................................................................................................... 1023

A.1.4 SNAP Packet Format................................................................................................. 1023

A.2 Packet Types for Packet Split Filtering ........................................................................................ 1023

A.2.1 Type 1.1: Ethernet (VLAN/SNAP) IP Packets ................................................................ 1024

A.2.2 Type 2: Ethernet, IPv6 ............................................................................................. 1033

A.2.3 Type 3: Reserved..................................................................................................... 1036

A.2.4 Type 4: NFS Packets ................................................................................................ 1036

A.3 IPsec Formats Run Over the Wire ..............................................................................................1041

A.3.1 AH Formats............................................................................................................. 1041

A.3.2 ESP Formats............................................................................................................ 1045

A.4 BCN Frame Format.................................................................................................................. 1050

A.5 FCoE Framing ......................................................................................................................... 1051

A.5.1 FCoE Frame Format.................................................................................................. 1051

A.5.2 FC Frame Format ..................................................................................................... 1054

Appendix B LESM - Link Establishment State Machine for the 82599 ......................... 1061

B.1 Background............................................................................................................................ 1061

B.2 Location in the NVM................................................................................................................. 1062

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