PCI EXPRESS BASE SPECIFICATION, REV. 4.0 VERSION 0.7
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8.2.1 Link Discovery and Configuration........................................................................ 1047
8.2.2 Attributes ............................................................................................................... 1048
8.2.3 Remote Register Access Protocol (RRAP): ........................................................... 1061
8.3 SYMBOL ENCODING, FRAMING AND SCRAMBLING .................................................... 1074
8.3.1 8b/10b Decode Rules ............................................................................................ 1074
8.3.2 Framing and Application of Symbols to LANES ................................................... 1074
8.3.3 Data Scrambling ................................................................................................... 1075
8.4 LINK INITIALIZATION AND TRAINING ......................................................................... 1075
8.4.1 Training Sequence (TS) Ordered Sets................................................................... 1076
8.4.2 Electrical Idle ........................................................................................................ 1082
8.4.3 EIEOS for M-PCIe ................................................................................................ 1082
8.4.4 Lane Polarity Inversion ........................................................................................ 1082
8.4.5 Fast Training Sequence (FTS) .............................................................................. 1082
8.4.6 LINK Data RATE .................................................................................................. 1083
8.4.7 LINK Width ........................................................................................................... 1083
8.4.8 LANE-to-LANE De-skew ...................................................................................... 1083
8.4.9 LINK Training and Status State Machine (LTSSM) ............................................. 1083
8.4.10 Entry to HIBERN8 ............................................................................................ 1105
8.5 RECEIVER ERROR ....................................................................................................... 1105
8.6 CLOCK TOLERANCE COMPENSATION ......................................................................... 1106
8.7 DYNAMIC LINK BANDWIDTH MANAGEMENT ........................................................... 1106
8.7.1 LINK Rate Series and Speed Management ........................................................... 1107
8.7.2 LINK Width Management ..................................................................................... 1107
8.7.3 Dynamic LINK Re-Configuration ......................................................................... 1107
8.8 M-PHY REGISTERS ................................................................................................... 1111
8.8.1 M-PHY Capability Registers ................................................................................. 1111
8.8.2 M-PHY Configuration Attributes .......................................................................... 1118
9 ELECTRICAL SUB-BLOCK........................................................................................ 1120
9.1 ELECTRICAL SPECIFICATION ORGANIZATION............................................................. 1120
9.2 INTEROPERABILITY CRITERIA .................................................................................... 1120
9.2.1 Data Rates ............................................................................................................. 1120
9.2.2 Refclk Architectures .............................................................................................. 1120
9.3 TRANSMITTER SPECIFICATION ................................................................................... 1120
9.3.1 Measurement Setup for Characterizing Transmitters ........................................... 1120
9.3.2 Voltage Level Definitions ...................................................................................... 1122
9.3.3 Tx Voltage Parameters ......................................................................................... 1123
9.3.4 Transmitter Margining ......................................................................................... 1132
9.3.5 Tx Jitter Parameters ............................................................................................. 1133
9.3.6 Data Rate Dependent Parameters ........................................................................ 1140
9.3.7 Tx and Rx Return Loss .......................................................................................... 1144
9.3.8 Transmitter PLL Bandwidth and Peaking ............................................................ 1145
9.3.9 Data Rate Independent Tx Parameters ................................................................. 1146
9.4 RECEIVER SPECIFICATIONS ........................................................................................ 1147
9.4.1 Receiver Stressed Eye Specification ..................................................................... 1147
9.4.2 Stressed Eye Test ................................................................................................... 1153
9.4.3 Common Receiver Parameters ............................................................................. 1161