高速数字接口自动化测试工程师指南

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"An Engineer's Guide to Automated Testing of High-Speed Interfaces" 是一本面向高速数字接口自动化测试的专业指南，由José Moreira和Hubert Werkmann撰写，旨在帮助工程师理解和解决在高吞吐率接口测试中遇到的挑战，特别是关于抖动和抖动测试的问题。这本书涵盖了高速数字接口测试的多个方面，适合从事相关研究和工作的人员学习。书中可能涉及的关键知识点包括： 1. **高速数字接口**：高速数字接口如PCIe、USB、HDMI等，它们在现代电子设备中起着至关重要的作用，允许快速数据传输。这些接口的设计和测试都需要深入理解信号完整性和电磁兼容性。 2. **抖动（Jitter）**：抖动是数字信号质量的一个关键参数，指的是信号在理想时间位置上的随机偏差。它会影响系统的可靠性和数据传输速率，对高速接口的性能至关重要。 3. **抖动测试**：测试抖动是为了评估系统是否能在预期的运行条件下正确处理信号。这涉及到测量和分析信号的定时不稳定性，以确定其是否符合规格要求。 4. **误码率（BER）**：误码率是衡量数据传输错误的一个指标，表示在一定时间内接收到的错误比特数与总传输比特数的比例。在高速接口测试中，低误码率通常意味着良好的系统性能。 5. **编码（Coding）**：在高速通信中，数据通常通过特定的编码方式（如8b/10b编码）来提高信号质量和纠错能力。编码可以影响抖动的表现和系统对抖动的敏感度。 6. **扰码（Scrambling）**：扰码是一种线性反馈移位寄存器技术，用于改善信号的功率谱密度，减少串扰并提高信道效率。在高速接口中，扰码可以改善信号质量并帮助应对噪声。 7. **自动化测试**：自动化测试是本书的重点，它涉及使用专用的测试平台和软件工具来自动执行测试序列，提高测试效率和准确性。自动化测试系统通常包括信号发生器、示波器、误码检测器等组件。 8. **信息存储和检索系统**：书中可能讨论了如何集成和管理测试数据，以及如何利用自动化系统进行长期的数据存储和检索，以便于故障排查和性能分析。 9. **知识产权（IP）注意事项**：作者强调了书中提及的所有商标和服务标志均已被适当地大写，这表明书中可能会讨论到各种工业标准和公司的专有技术，要求读者尊重知识产权。这本书提供了高速接口自动化测试的全面指导，涵盖了从基础理论到实际应用的各种关键概念和技术，对于设计、验证和测试这些接口的工程师来说是一份宝贵的参考资料。

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Contents xv

E.1.4

Measuring the Return Loss with a TDR 495

E.2 TDT 497

E.2.1 Measuring the Step Response 497

E.2.2 Measuring the Insertion Loss with a TDT 498

E.2.3 Measuring Crosstalk Using a TDT and an Extra Sampler 498

E.3 Differential TDR/TDT Measurements 499

References 501

F S-Parameters 503

.1 Simulating and Synthesizing Time-Domain Responses from

S-Parameters 509

F.2 S-Parameters of Coupled Differential Pairs and Structures 511

References 513

G Engineering CAD Tools 515

G.1

Circuit Simulators 515

G.2 3D EM Field Solvers 518

G.3 2D Planar Field Solvers 518

G.4 Power Integrity 520

G.5 Model Generation 521

G.6 Other Tools 521

References 524

H Test Fixture Evaluation and Characterization 525

H.1

Measuring the Test Fixture Performance 525

H.1.1 Test Coupons 527

H.1.2 Test Fixture Socket and Socket Via Field Probing 529

H.2 Measuring the Test Fixture Power Distribution Network 535

References 540

I Jitter Injection Calibration 543

I.1

Sinusoidal Jitter Injection Calibration 543

I.1.1 The J

Bessel Approach 544

I.1.2 The RJ Subtraction Approach 548

xviii

An Engineer’s Guide to Automated Testing of High-Speed Interfaces

the

y are.

The target audience of this book are mainly test engineers working on

design veriﬁcation, characterization, and production testing of multigigabit

I/O interfaces. However, the book provides a general overview over the

challenges these test engineers face in their daily work with high-speed

devices that can be helpful also for chip designers and product engineers to

minimize these challenges using appropriate DfT and device test strategies to

ensure sufﬁcient device quality with less test implementation effort.

After introducing the challenges of high-speed digital testing on ATE

in Chapter 1, we provide a general introduction to high-speed digital signals

and related topics in Chapter 2 to set the basic framework to understand the

following chapters.

The underlying basis for this book is the high-speed I/O digital

standards that evolved in the past years. In Chapter 3, we discuss some

of these standards. We selected the standards that are covered with regard

to the general test requirements and challenges they represent for ATE

implementations. The chosen standards reﬂect a cross-section of the current

high-speed I/O interfaces in the market with respect to test requirements.

In this chapter we do not want to give a very detailed description and test

implementation examples for the dedicated interface. The main purpose is to

extract the general architectural characteristics for each interface that deﬁne

the type of tests that need to be implemented and can be leveraged to other

interfaces that use similar architectural implementations.

After this, we present the basics of ATE systems and instrumentation in

Chapter 4 with emphasis on the critical instrumentation for high-speed digital

applications like, for example, digital pin electronics cards, sampler/digitizer

cards, and power supplies. One of the core chapters of the book is Chapter 5

that covers the details of key measurements for high-speed I/O interfaces and

the options a test engineer has to implement these measurements on an ATE

system.

Chapter 6 focuses on how high-speed I/O interfaces can be tested

efﬁciently in a production test environment. The key discussion in this chapter

deals with at-speed loopback testing. Characterization and test of high-speed

digital I/Os often requires complementing an ATE with external measurement

instruments for some dedicated tests. Chapter 7 presents some of the bench

instrumentation that is relevant for engineers working on high-speed digital

applications on ATE and also some of the related accessories.

One of the topics that commonly is recognized as a key bottleneck

for the ability to test and characterize high-speed digital interfaces on an

ATE is the electrical interfacing between the ATE pin electronics and the

DUT. Chapter 8 covers this bottleneck and discusses ATE test ﬁxture design

eface xix

including

associated topics like sockets and wafer probing.

Last but not least, we discuss some advanced topics on high-speed

digital testing with ATE in Chapter 9. These topics include the deﬁnition of

EPA/OTA, the importance of linearity, focus calibration, and the important

topics of de-embedding and test ﬁxture loss compensation through equaliza-

tion.

In the appendices of the book, we cover several additional topics that

are not directly related to the test of high-speed devices itself. However,

these topics are helpful to understand the background of some of the test

requirements and test implementations that are presented in the main chapters

of the book.

Appendix A provides a brief overview of the Gaussian distribution and

some examples of obtaining analytical results that are relevant for high-speed

digital applications.

Appendix B presents a detailed description of the dual Dirac jitter model

and the associated random and deterministic jitter separation algorithm.

Appendix C presents an overview of pseudo-random bit sequences and

other important data patterns.

Appendix D discusses the topics of encoding, scrambling, disparity, and

error correction that are required to understand the implementation of some

of the high-speed digital standards.

Appendix E provides an introduction to the topic of time domain reﬂec-

tometry and transmission that is important for test ﬁxture characterization.

Appendix F introduces the concept of S-parameters that are again

important for test ﬁxture characterization and modeling.

Appendix G provides an overview of the different simulation tools that

are relevant for high-speed digital applications, especially for test ﬁxture

design.

Appendix H presents several approaches to characterize a manufactured

test ﬁxture electrical performance, not only regarding the high-speed signal

paths but also the power distribution network.

Appendix I discusses the challenge of calibrating the amount of jitter

injected by an ATE driver into the device under test (DUT) since receiver

jitter tolerance is a key part in some of the high-speed digital standards.

Acknowledgments

We ﬁrst thank Heidi Barnes, Hideo Okawara, and Bernhard Roth from Verigy

and Michael Comai from AMD for contributing to the sections on test ﬁxture

design, sampler/digitizer ATE card, data eye proﬁle, active equalization, and

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