系统级ESD设计实践：白皮书3第二部分详解

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"White Paper 3（2019 Rev 2.0）系统级 ESD 第二部分：有效 ESD 稳健设计的实施，是关于系统级静电放电（ESD）设计的重要文档，强调了在系统层面分析 ESD 对组件交互影响的重要性。这份153页的完整英文电子版白皮书由 Industry Council on ESD Target Levels 发布，旨在推动更高效、更全面的 ESD 设计方法。" 本文档主要探讨了系统级 ESD 设计的关键概念，指出传统的认为所有组件只要超过一定 ESD 水平就能确保系统稳健的观点是错误的。白皮书分为两部分，Part I 揭示了供应商与原始设备制造商（OEM）之间关于系统级 ESD 的常见误解，并介绍了称为系统高效 ESD 设计（SEED）的组件/系统协同设计方法。SEED 方法是一种针对系统接口防止永久性故障的综合 ESD 设计策略。在 Part II 中，白皮书扩展了对系统 ESD 理解的全面分析，涵盖了不同类型的系统故障，包括硬故障（永久损坏）、软故障（暂时性功能丧失）和电磁干扰（EMI）。这部分详细阐述了如何通过适当的组件表征和仿真数据来评估整个系统的 ESD 性能。这种方法强调了在设计阶段考虑 ESD 影响的必要性，以便在实际操作中减少潜在的问题。此外，文档还可能涵盖了 ESD 保护设计的基本原则，例如防护电路的设计、材料选择、接地策略、信号完整性以及与 EMI 控制的协同工作。作者可能会讨论如何通过仿真工具模拟 ESD 事件，以及如何利用这些工具来优化设计。同时，文档可能还包括了测试方法和标准，比如 IEC 61000-4-2（人体模型）和 ANSI/ESD STM5.1（机器模型），以及 JEDEC 的相关标准，以确保设计符合行业规范。总结起来，这份白皮书提供了对系统级 ESD 问题的深入洞察，指导工程师在设计早期就考虑 ESD 防护，从而实现更加稳健和可靠的电子系统。通过系统方法和仿真技术，设计师能够更好地理解 ESD 敏感性，并采取适当措施避免潜在的故障模式，提高产品的质量和可靠性。这对于任何涉及电子设备设计和制造的专业人士来说，都是极其宝贵的资源。

Industry Council on ESD Target Levels 16

Executive Summary

Overview

White Paper 3 Part II, while establishing the complex nature of system level ESD, proposes that

an efficient ESD design can only be achieved when the interaction of the various components

under ESD conditions are analyzed at the system level. This objective requires an appropriate

characterization of the components and a methodology to assess the entire system using

simulation data. This is applicable to system failures of different categories (such as hard, soft,

and electromagnetic interference (EMI)). This type of systematic approach is long overdue and

represents an advanced design approach which replaces the misconception, as discussed in detail

in White Paper 3 Part I, that a system will be sufficiently robust if all components exceed a certain

ESD level.

In the first step, a method for categorizing the failure types has been introduced. An advanced

characterization and simulation approach is discussed through examples. However, a full design

flow cannot be established without a common effort across the electronic industry involving

IC suppliers, suppliers of discrete protection components and original equipment

manufacturers (OEMs) as well as tool vendors. This paper identifies existing tools with both

simulations and scanning techniques that are applicable for this purpose and calls out fields for

further development.

Equally important is the notion that efficient system ESD design can ideally be achieved by

improved communication between the IC supplier, the OEM and the system builder. As

technologies advance even further, and as systems become more complex under various

applications, this shared responsibility is expected to gradually shift more towards system design

expertise.

Understanding Component to System ESD

Towards achieving the goals mentioned above, it is first important to decouple the component

ESD requirements from system level ESD design. White Papers 1 and 2 established that

component electrostatic discharge (ESD) levels can be safely reduced to practical levels with

basic ESD control methods that are mandatory in every production area. We have also established

that these ESD target levels enable fabrication of integrated circuits (ICs) with on-time delivery

(in billions of units) for electronic systems in consumer applications with high circuit

performance. The general perception has been that component ESD (for example, human body

model (HBM)) is a prerequisite for good system level ESD robustness. But this misconception

once again needs to be clarified, as shown below in Figure 1, system level ESD and component

ESD are not correlated with each other.

Industry Council on ESD Target Levels 17

Figure 1: Comparison of IC level and system level ESD failure threshold of various systems (A-J) showing that HBM

protection is not related to System level ESD robustness

In fact, at the system level, ESD robustness is a much more complex issue requiring a deeper

understanding to address the ESD protection requirements for electronic systems such as laptops,

cell phones, printers and home computers. These system complexities come about as a result of

protecting the external interfaces, such as the universal serial bus (USB), to the outside world.

Such systems, after encountering the more severe ESD pulses defined by the IEC standard, can

lead to hard or soft failures. As introduced in White Paper 3 Part I, the basic version of system-

efficient ESD design (SEED) addresses hard failures related to IC pins with a direct external

interface, soft failures, which are more frequently reported, are challenging to understand and

overcome. In this latter case, addressing soft failures requires an extension of the SEED approach

to other failure mechanisms that include latch-up and EMI effects. In this document, the steps to

categorize the different failure mechanisms, and the appropriate characterization and simulation

methodologies, are identified through various forms of Advanced SEED.

Communication and Strategy

This white paper documents a rigorous approach to describing the challenges related to all

categories of system level ESD failures that can arise from energy injection due to the IEC

contact pulse stress, as well as from electromagnetic compatibility (EMC) and EMI effects. To

classify these fails and to provide a common terminology, three categories of fails have been

introduced:

- SEED Category 1 (physical damage due to pulse energy)

- SEED Category 2 (damage or interference of function due to transient latch-up)

- SEED Category 3 (interference of function by noise or bursts on supply net and signal

lines)

Industry Council on ESD Target Levels 18

Understanding these different categories of failures is an important part of addressing the

appropriate solutions. Thus, one main objective is to close the existing communication gap

between OEMs and IC providers by involving the expertise of both OEMs and system design

experts. As a result, the completion of this second phase of White Paper 3 required the

participation and contributions from world class experts on the art of system level ESD

phenomena and protection techniques.

One of the challenges which remains elusive is the trade-off between cost, performance,

robustness, and time-to-market. This white paper also addresses these issues, bringing forth a

dialogue between the IC supplier, customer, and the system designer.

Implementation of Advanced Tools

White Paper 3 Part II specifically covers in detail an overview of system ESD stress application

methods, system diagnostic techniques to detect hard or soft failures, and the application of

tools for susceptibility scanning. For example, as illustrated in Figure 2, these types of advanced

tools can be used to differentiate the characteristics of products and enable proper system

protection methodology.

Figure 2: Susceptibility scanning using pulse techniques on Product A (left) and Product B (right)

(Courtesy of Amber Precision Instruments)

Along the lines of communication and interaction, IC suppliers and system designers can share

their knowledge of tools and their applications. For example, suppliers would provide a single

definition, high quality model of their input/output (IO). Then OEMs would use analytical tools to

integrate the IC’s IO models into their system models for system level stress analysis. These tools

will not reach their full potential unless the data they collect can be used within the standard

design flow for an electronic system. For these to be effective, model files such as input/output

buffer information specification (IBIS) and simulation programs with integrated circuit emphasis

(SPICE), which describe the electrical properties of components, need to be enhanced to describe

component behavior in the ESD range. The general framework for such modeling has been

defined through IEC 61433-6 and the detailed models around the integrated circuit itself, such as

discussed above, are currently in definition based on an industry wide investigation performed by

Industry Council on ESD Target Levels 19

ESDA WG26 on system level ESD modeling. Suppliers of components, ranging from integrated

circuits to ESD protection components also need to characterize their products in the appropriate

ESD range.

Impact from the Technology Roadmap

Finally, we bring into focus that IC technology and related circuit speeds will increasingly have

an impact on system designs. This roadmap will cover market segments ranging from information

technology (IT), communications, automotive electronics, IC package technology development to

advances in board and assembly technologies. The cost of ESD must be considered along with

all development and innovation; the industry must decide who should bear the cost of ESD

design and its pressure on production schedules and time to market

System level ESD will continue to be a challenge in the future. The dilemma of meeting

technology demands for speed and performance will inevitably require either the development of

more effective shielding or innovation of novel on-board protection solutions.

Conclusions

In summary, this white paper has pointed out the necessary framework required for

comprehensive improvement in the first time success rate of ESD robust system designs. A

number of helpful tools and techniques already exist. However, standardization between IC

suppliers, PCB protection device suppliers and system designers requires common models,

common methods and compatible simulation tools in order to meet the goal of better ESD design

capability. None of this will occur without a great deal of communication between EDA tool

vendors, component suppliers and system designers.

Finally, this document has provided a major step forward in identifying and understanding the

technical issues. An important message to remember is that the current focus on component

ESD performance must shift towards improving system level ESD performance. That is,

while minimum component ESD levels provide for safe component handling, the bulk of

future research and development efforts should be directed towards system level ESD to

reach a day when a high first pass success rate in system level ESD design is

straightforward.

Industry Council on ESD Target Levels 20

Chapter 1: Introduction & Purpose

Robert Ashton, ON Semiconductor

Charvaka Duvvury, Texas Instruments

1.0 History of the Industry Council on ESD Target Levels

The Industry Council on ESD Target Levels (Council) was formed in 2006 to address a growing

disconnect between original equipment manufacturers (OEMs) and manufacturers of integrated

circuits (ICs) with regard to electrostatic discharge (ESD). The competitive environment requires

that OEMs create products with higher performance in ever smaller form factors while

maintaining and improving reliability and offering the products at competitive prices. This

progress was made possible by imposing the following improvements in ICs; higher levels of

functionality, higher speeds, smaller component size and lower power. That is, the burden of

higher performance has been transferred to the IC suppliers, who must achieve these

improvements through enhancements in their chip designs. IC manufacturers have been able to

make these improvements by employing new IC technologies with smaller feature sizes to

improve functionality and speed and lower working voltages to prevent wear-out of the circuit

and maintain reasonable power levels.

OEMs of course need these improvements, but they do not want them at the cost of reliability and

yield. OEMs therefore maintained the same quality and reliability requirements on ICs produced

in the latest technology as they had for a more mature product. One of these requirements was for

the ESD robustness of ICs. 2 kV of human body model (HBM) robustness had long been a de

facto standard and 500 V of charged device model (CDM) robustness was becoming a similar

requirement. Also, there was an unintended, albeit perceived important, requirement that the ICs

must simultaneously meet 200 V for the machine model (MM). However, starting around the 90

nm technology node, IC manufacturers were finding it increasingly difficult, and sometimes

impossible, to consistently meet these requirements. The smaller feature sizes, lower operating

voltages and high speed signal requirements of ICs were shrinking the design window available

for ESD protection. IC manufacturers, however, knew that 2 kV HBM and 500 V CDM levels

were not needed. HBM and CDM tests are performed to ensure that ICs can survive manufacture

in an ESD controlled manufacturing facility. Experience has shown that with basic ESD control

procedures, ICs with far lower HBM and CDM levels could be handled. Furthermore, without

basic ESD controls, robustness far beyond 2 kV HBM and 500 V CDM will not survive.

Attempting to meet 2 kV HBM and 500 V CDM was therefore costing the industry millions of

dollars in redesigns and delays to market without any benefit to the industry.

The Council was formed to show the electronics industry that lowering ESD levels from 2000 V

HBM and 500 V CDM was not only possible without sacrificing quality and reliability, but also

the right thing to do. “White Paper 1: A Case for Lowering Component Level HBM/MM ESD

Specifications and Requirements” [1] demonstrated why it was becoming more difficult to design

high levels of HBM performance in advanced technologies and presented data that proved lower

HBM levels do not lead to higher levels of failure. White Paper 1 also showed that designing for

HBM would guarantee adequate levels of intrinsic MM performance and that specifically testing

for MM was not necessary. “White Paper 2: A Case for Lowering Component Level CDM ESD

Specifications and Requirements” [2] made a similar case for CDM levels below 500 V by

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系统级ESD设计实践：白皮书3第二部分详解

White Paper 3：2019(Rev 2.0) System Level ESD Part II：Implementa

White Paper 3：2019(Rev 2.0) System Level ESD Part II：Implementation of Effective ESD Robust Designs - 完整英文电子版（153页）.pdf

White Paper 3：2010(Rev 1.0) System Level ESD Part I：Common Misconceptions and Recommended Basic Approaches - 完整英文电子版（116页）.pdf

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white-space：pre-line 和 white-space：pre同时写会是什么效果

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