Xilinx AXI_BRAM IP核：高性能内存控制器

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"Xilinx AXI_BRAM IP核是Xilinx公司提供的一种软逻辑CORE IP，用于嵌入式开发工具包（EDK）。该IP核设计为AXI接口的从设备，能够与AXI互连和系统主设备集成，实现与本地BRAM的通信。它支持单次和突发交易，优化了性能，适用于高性能应用。特性： - 支持AXI4（内存映射）从接口 - 低延迟内存控制器 - 分离的读写通道接口，利用双口FPGA BRAM技术 - 可配置的BRAM数据宽度（32位、64位和128位） - 支持递增模式下的最大256次数据传输的突发操作 - 支持2、4、8和16个数据拍的WRAP突发操作 - 支持AXI窄写和未对齐的写突发传输 - 与Xilinx的其他AXI接口兼容 AXI_BRAM IP核的使用使得在FPGA设计中访问存储器变得更加方便和高效。它的AXI4从接口遵循AXI协议标准，提供了内存映射的访问方式，可以处理简单的读写操作以及复杂的突发传输。低延迟特性使其在实时应用中表现出色，确保数据传输的快速响应。分离的读写通道接口是AXI_BRAM IP核的一个关键特点，它允许同时进行读取和写入操作，这对于需要高速并发读写的系统来说至关重要。此外，通过配置BRAM数据宽度，可以适应不同带宽需求的应用场景。支持不同的突发模式（INCR和WRAP）使AXI_BRAM IP核能够灵活地处理各种数据流，例如连续的数据块传输或循环数据访问模式。AXI窄写和未对齐的写突发传输功能则增强了其对不规则数据访问的支持，这对于处理非结构化数据或边界情况非常有用。 Xilinx AXI_BRAM IP核是一个强大且灵活的内存控制器，适用于需要高效访问内部BRAM资源的FPGA设计。它能够无缝地融入基于AXI的系统架构中，为高性能、低延迟的内存访问提供了解决方案。设计者可以根据具体需求配置IP核的各项参数，以满足特定应用的性能和功能要求。"

DS777 December 14, 2010 www.xilinx.com 7

Product Specification

LogiCORE IP AXI BRAM Controller (v1.01a)

S_AXI_WREADY W O ‘0’

AXI write data ready: indicates that the AXI BRAM Controller is

ready to accept the write data and strobes.

‘0’ = AXI BRAM Controller not ready

‘1’ = AXI BRAM Controller is ready

AXI Write Response Channel Signals (B)

S_AXI_BID

[C_S_AXI_ID_WIDTH-1:0]

BOZeros

AXI write data response ID: Identification tab of the write

response. BID matches the AWID value of the write transaction

to which the AXI BRAM Controller is responding.

S_AXI_BRESP [1:0] B O Zeros

AXI write response: Indicates the status of the write

transaction. The supported responses of the AXI BRAM

Controller are OKAY (SLVERR and EXOKAY to be supported

in a future release).

S_AXI_BVALID B O ‘0’

AXI write response valid: Asserted by the AXI BRAM Controller

to indicate a valid write response is available.

‘0’ = write response not available

‘1’ = write response is available

S_AXI_BREADY B I

Write response ready: Indicates the master requesting the

write operation can accept the response information.

‘0’ = AXI master not ready

‘1’ = AXI master is ready

AXI Read Address Channel Signals (AR)

S_AXI_ARID

[C_S_AXI_ID_WIDTH-1:0]

AR I

AXI address read ID: Identification tag for the read address

group of signals.

S_AXI_ARADDR

[C_S_AXI_ADDR_

WIDTH-1:0]

AR I

AXI read address: The address provides the initial address of

the read burst transaction. Only the start address of the burst is

provided and the control signals indicate the address detail and

calculation for each transfer in the burst.

S_AXI_ARLEN [7:0] AR I

AXI address read burst length: The burst length gives the exact

number of transfers in a burst. Determines the number of data

transfers associated with the read address.

S_AXI_ARSIZE [2:0] AR I

AXI address read burst size: Indicates the size of each transfer

in the burst.

S_AXI_ARBURST [1:0] AR I

AXI address read burst type: Indicates the burst type, coupled

with the size information, details how the address for each

transfer within the burst is calculated.

S_AXI_ARLOCK AR I

AXI read address lock signal: Provides information about

atomic operation transfers. Unused at this time, but listed here

for future implementation and support.

S_AXI_ARCACHE [4:0] AR I

AXI read address cache control signa: Provides information

about bufferable, cacheable, and allocation attributes.

Unused at this time, but listed here for future implementation

and support.

S_AXI_ARPROT [3:0] AR I

AXI read address protection signal: Unused at this time, but

listed here for future implementation and support.

Tab l e 1 : I/O Signal Description (Cont’d)

Signal Name Interface

Signal

Type

Init

Status

Description

DS777 December 14, 2010 www.xilinx.com 8

Product Specification

LogiCORE IP AXI BRAM Controller (v1.01a)

S_AXI_ARVALID AR I

AXI read address valid: Indicates that the valid read address

and control information is available.

‘0’ = address and control NOT available

‘1’ = address and control data is available

The address and control information remains stable until the

acknowledge signal (AWREADY) is asserted (active high).

S_AXI_ARREADY AR O ‘0’

AXI read address ready: Indicates that the AXI BRAM

Controller has accepted the read channel address and

associated control signals.

‘0’ = AXI BRAM Controller not ready

‘1’ = AXI BRAM Controller is ready

AXI Read Data Channel Signals (B)

S_AXI_RID

[C_S_AXI_ID_WIDTH-1:0]

BOZeros

AXI read data response ID: Identification tab of the read

response. RID matches the ARID value of the read address

transaction to which the AXI BRAM Controller is responding.

S_AXI_RDATA

[C_S_AXI_DATA_

WIDTH-1:0]

B O Zeros AXI read data.

S_AXI_RRESP [1:0] B O Zeros

Note: AXI read response: Indicates the status of the read

transfer. AXI BRAM Controller supports the OKAY and

SLVERR responses (EXOKAY reserved for future support).

S_AXI_RLAST B O ‘0’

AXI read data last signal: Indicates the last transfer in a read

burst.

S_AXI_RVALID B O ‘0’

AXI read valid: Asserted by the AXI BRAM Controller to

indicate the required read data is available and the read

transfer can complete.

‘0’ = read data not available

‘1’ = read data is available

S_AXI_RREADY B I

Read ready: Indicates the requesting master can accept the

read data and response information.

‘0’ = AXI master not ready

‘1’ = AXI master is ready

BRAM Signals

BRAM_Rst_A BRAM O ‘0’ Port A BRAM active high reset.

BRAM_Clk_A BRAM O ‘0’

Port A BRAM clock: Connected to AClk with same frequency,

same phase alignment.

BRAM_En_A BRAM O ‘0’ BRAM Port A (write port) enable signal. Active High.

BRAM_WE_A

[C_S_AXI_DATA_

WIDTH/8-1:0]

BRAM O Zeros

BRAM Port A (write port) write enable signal: Active High. Byte

wise signal to width of BRAM.

BRAM_Addr_A

[C_S_AXI_ADDR_

WIDTH-1:0]

BRAM O Zeros

BRAM Port A (write port) address bus: Bus is sized according

to the parameter, C_S_AXI_ADDR_WIDTH.

BRAM_WrData_A

[C_S_AXI_DATA_

WIDTH-1:0]

BRAM O Zeros

BRAM Port A (write port) write data bus. Size of BRAM write

data width is equal to size of AXI slave port connection to the

AXI BRAM Controller.

Tab l e 1 : I/O Signal Description (Cont’d)

Signal Name Interface

Signal

Type

Init

Status

Description

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