STM32F103x4微控制器数据手册：性能特点和技术规格

需积分: 10 3 浏览量更新于2024-07-22 1 收藏 1.04MB PDF 举报

STM32F103T4微控制器数据手册 STM32F103T4是STMicroelectronics公司出品的低密度性能线路微控制器，基于ARM Cortex-M3 CPU核心，具有16KB或32KB的Flash存储器，USB、CAN、6个定时器、2个模拟数字转换器（ADC）和6个通信接口等特性。核心特性 STM32F103T4的核心是ARM Cortex-M3 CPU，最高工作频率为72MHz，性能高达1.25 DMIPS/MHz（Dhrystone 2.1），具有单周期乘法和硬件除法功能。存储器 STM32F103T4具有16KB或32KB的Flash存储器和6KB或10KB的SRAM存储器，满足各种应用的存储需求。时钟、复位和电源管理 STM32F103T4具有2.0到3.6V的应用电源和I/O电压，支持POR、PDR和可编程电压检测（PVD），具有4-16MHz的晶振荡器、内部8MHz的工厂调整RC振荡器、内部40kHz的RC振荡器、PLL用于CPU时钟和32kHz的振荡器用于RTC（实时时钟）和校准。低功耗 STM32F103T4具有低功耗设计，支持Sleep、Stop和Standby模式，具有VBAT电源用于RTC和备份寄存器。模拟数字转换器 STM32F103T4具有两个12位、1µs的模拟数字转换器（ADC），最高支持16个通道，转换范围为0到3.6V，具有双样本保持能力和温度传感器。直接存储器访问（DMA） STM32F103T4具有7通道的DMA控制器，支持timers、ADC、SPIs、I2Cs和USARTs等外围设备。输入/输出端口 STM32F103T4具有upto 51个快速I/O端口，所有I/O端口都可以映射到16个外部中断上。 STM32F103T4微控制器是低密度性能线路的代表，具有强大的处理能力、丰富的外围设备和低功耗设计，适合各种嵌入式系统应用。

STM32F103x4, STM32F103x6 Description

Doc ID 15060 Rev 3 13/80

2.3 Overview

2.3.1 ARM

Cortex™-M3 core with embedded Flash and SRAM

The ARM Cortex™-M3 processor is the latest generation of ARM processors for embedded

systems. It has been developed to provide a low-cost platform that meets the needs of MCU

implementation, with a reduced pin count and low-power consumption, while delivering

outstanding computational performance and an advanced system response to interrupts.

The ARM Cortex™-M3 32-bit RISC processor features exceptional code-efficiency,

delivering the high-performance expected from an ARM core in the memory size usually

associated with 8- and 16-bit devices.

The STM32F103xx performance line family having an embedded ARM core, is therefore

compatible with all ARM tools and software.

Figure 1 shows the general block diagram of the device family.

2.3.2 Embedded Flash memory

16 or 32 Kbytes of embedded Flash is available for storing programs and data.

2.3.3 CRC (cyclic redundancy check) calculation unit

The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit

data word and a fixed generator polynomial.

Among other applications, CRC-based techniques are used to verify data transmission or

storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of

verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of

the software during runtime, to be compared with a reference signature generated at link-

time and stored at a given memory location.

2.3.4 Embedded SRAM

Six or ten Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0 wait

states.

2.3.5 Nested vectored interrupt controller (NVIC)

The STM32F103xx performance line embeds a nested vectored interrupt controller able to

handle up to 43 maskable interrupt channels (not including the 16 interrupt lines of

Cortex™-M3) and 16 priority levels.

● Closely coupled NVIC gives low-latency interrupt processing

● Interrupt entry vector table address passed directly to the core

● Closely coupled NVIC core interface

● Allows early processing of interrupts

● Processing of late arriving higher priority interrupts

● Support for tail-chaining

● Processor state automatically saved

● Interrupt entry restored on interrupt exit with no instruction overhead

Description STM32F103x4, STM32F103x6

14/80 Doc ID 15060 Rev 3

This hardware block provides flexible interrupt management features with minimal interrupt

latency.

2.3.6 External interrupt/event controller (EXTI)

The external interrupt/event controller consists of 19 edge detector lines used to generate

interrupt/event requests. Each line can be independently configured to select the trigger

event (rising edge, falling edge, both) and can be masked independently. A pending register

maintains the status of the interrupt requests. The EXTI can detect an external line with a

pulse width shorter than the Internal APB2 clock period. Up to 51 GPIOs can be connected

to the 16 external interrupt lines.

2.3.7 Clocks and startup

System clock selection is performed on startup, however the internal RC 8 MHz oscillator is

selected as default CPU clock on reset. An external 4-16 MHz clock can be selected, in

which case it is monitored for failure. If failure is detected, the system automatically switches

back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full

interrupt management of the PLL clock entry is available when necessary (for example on

failure of an indirectly used external crystal, resonator or oscillator).

Several prescalers allow the configuration of the AHB frequency, the high-speed APB

(APB2) and the low-speed APB (APB1) domains. The maximum frequency of the AHB and

the high-speed APB domains is 72 MHz. The maximum allowed frequency of the low-speed

APB domain is 36 MHz. See Figure 2 for details on the clock tree.

2.3.8 Boot modes

At startup, boot pins are used to select one of three boot options:

● Boot from User Flash

● Boot from System Memory

● Boot from embedded SRAM

The boot loader is located in System Memory. It is used to reprogram the Flash memory by

using USART1. For further details please refer to AN2606.

2.3.9 Power supply schemes

● V

= 2.0 to 3.6 V: external power supply for I/Os and the internal regulator.

Provided externally through V

pins.

● V

SSA

, V

DDA

= 2.0 to 3.6 V: external analog power supplies for ADC, reset blocks, RCs

and PLL (minimum voltage to be applied to V

DDA

is 2.4 V when the ADC is used).

DDA

and V

SSA

must be connected to V

and V

, respectively.

● V

BAT

= 1.8 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and backup

registers (through power switch) when V

is not present.

For more details on how to connect power pins, refer to Figure 10: Power supply scheme.

2.3.10 Power supply supervisor

The device has an integrated power-on reset (POR)/power-down reset (PDR) circuitry. It is

always active, and ensures proper operation starting from/down to 2 V. The device remains

STM32F103x4, STM32F103x6 Description

Doc ID 15060 Rev 3 15/80

in reset mode when V

is below a specified threshold, V

POR/PDR

, without the need for an

external reset circuit.

The device features an embedded programmable voltage detector (PVD) that monitors the

DDA

power supply and compares it to the V

PVD

threshold. An interrupt can be

generated when V

DDA

drops below the V

PVD

threshold and/or when V

DDA

is higher

than the V

PVD

threshold. The interrupt service routine can then generate a warning

message and/or put the MCU into a safe state. The PVD is enabled by software.

Refer to Table 11: Embedded reset and power control block characteristics for the values of

POR/PDR

and V

PVD

2.3.11 Voltage regulator

The regulator has three operation modes: main (MR), low power (LPR) and power down.

● MR is used in the nominal regulation mode (Run)

● LPR is used in the Stop mode

● Power down is used in Standby mode: the regulator output is in high impedance: the

kernel circuitry is powered down, inducing zero consumption (but the contents of the

registers and SRAM are lost)

This regulator is always enabled after reset. It is disabled in Standby mode, providing high

impedance output.

2.3.12 Low-power modes

The STM32F103xx performance line supports three low-power modes to achieve the best

compromise between low power consumption, short startup time and available wakeup

sources:

● Sleep mode

In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can

wake up the CPU when an interrupt/event occurs.

● Stop mode

The Stop mode achieves the lowest power consumption while retaining the content of

SRAM and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI RC

and the HSE crystal oscillators are disabled. The voltage regulator can also be put

either in normal or in low power mode.

The device can be woken up from Stop mode by any of the EXTI line. The EXTI line

source can be one of the 16 external lines, the PVD output, the RTC alarm or the USB

wakeup.

● Standby mode

The Standby mode is used to achieve the lowest power consumption. The internal

voltage regulator is switched off so that the entire 1.8 V domain is powered off. The

PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering

Standby mode, SRAM and register contents are lost except for registers in the Backup

domain and Standby circuitry.

The device exits Standby mode when an external reset (NRST pin), an IWDG reset, a

rising edge on the WKUP pin, or an RTC alarm occurs.

Note: The RTC, the IWDG, and the corresponding clock sources are not stopped by entering Stop

or Standby mode.

Description STM32F103x4, STM32F103x6

16/80 Doc ID 15060 Rev 3

2.3.13 DMA

The flexible 7-channel general-purpose DMA is able to manage memory-to-memory,

peripheral-to-memory and memory-to-peripheral transfers. The DMA controller supports

circular buffer management avoiding the generation of interrupts when the controller

reaches the end of the buffer.

Each channel is connected to dedicated hardware DMA requests, with support for software

trigger on each channel. Configuration is made by software and transfer sizes between

source and destination are independent.

The DMA can be used with the main peripherals: SPI, I

C, USART, general-purpose and

advanced-control timers TIMx and ADC.

2.3.14 RTC (real-time clock) and backup registers

The RTC and the backup registers are supplied through a switch that takes power either on

supply when present or through the V

BAT

pin. The backup registers are ten 16-bit

registers used to store 20 bytes of user application data when V

power is not present.

The real-time clock provides a set of continuously running counters which can be used with

suitable software to provide a clock calendar function, and provides an alarm interrupt and a

periodic interrupt. It is clocked by a 32.768 kHz external crystal, resonator or oscillator, the

internal low-power RC oscillator or the high-speed external clock divided by 128. The

internal low-power RC has a typical frequency of 40 kHz. The RTC can be calibrated using

an external 512 Hz output to compensate for any natural crystal deviation. The RTC features

a 32-bit programmable counter for long-term measurement using the Compare register to

generate an alarm. A 20-bit prescaler is used for the time base clock and is by default

configured to generate a time base of 1 second from a clock at 32.768 kHz.

2.3.15 Timers and watchdogs

The low-density STM32F101xx performance line devices include an advanced-control timer,

two general-purpose timers, two watchdog timers and a SysTick timer.

Table 4 compares the features of the advanced-control and general-purpose timers.

Table 4. Timer feature comparison

Timer

Counter

resolution

Counter

type

Prescaler

factor

DMA request

generation

Capture/compare

channels

Complementary

outputs

TIM1 16-bit

Up,

down,

up/down

Any integer

between 1

and 65536

Ye s 4 Ye s

TIM2,

TIM3

16-bit

Up,

down,

up/down

Any integer

between 1

and 65536

Ye s 4 N o

剩余79页未读，继续阅读

yangjian_1991

粉丝: 0
资源: 2

STM32F103x4微控制器数据手册：性能特点和技术规格

STM32F103系列中文数据手册

STM32F103x46_DS_CH_V2(2).pdf

stm32f103xxx.pdf

ARM Cortex-M3 系列 STM32F103 选型表

STM32F103驱动TSL1401线性CCD模块.rar

STM32选型指南，是工程师最好的M3选型手册

STM32 F1-F2-F4 比较.pdf

STM32103手册.pdf

【优化流量】基于matlab遗传算法GA求解OD流量优化问题【含Matlab源码 9159期】.mp4

基于深度学习YOLOv9实现道路红绿灯行人车辆(8类)识别检测系统python源码+详细教程+模型+数据集+评估指标曲线.zip

最新资源