NXP i.MX6ULL 工业级微处理器数据手册

IMX6ULL

数据手册

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"IMX6ULL是恩智浦半导体（NXPSemiconductors）推出的一款工业级微处理器，其数据手册详细介绍了该芯片的技术规格和订购信息。这款处理器主要针对连接设备市场，尤其注重多媒体处理和高效能。" 本文将深入探讨i.MX6ULL处理器的关键特性、应用领域以及技术细节。 i.MX6ULL处理器系列是恩智浦在集成多媒体处理产品上的最新成果，它以高效率和高性能为核心，搭载了单核Arm Cortex-A7内核，工作频率最高可达792MHz。这一特性使得i.MX6ULL在处理计算密集型任务时表现出色，同时保持低功耗，非常适合需要长时间运行的电池供电设备。处理器内部集成了电源管理模块，降低了外部电源供应的复杂性，并简化了电源排序流程，这对于优化系统能耗和稳定性至关重要。此外，i.MX6ULL家族的每个成员都提供了多种内存接口选项，如低功耗双倍数据速率（LPDDR）内存，这种内存类型在保证速度的同时，显著降低了功耗，适合对能耗敏感的应用场景。在封装方面，i.MX6ULL提供了两种尺寸的MAPBGA封装：14x14mm, 0.8mm间距和9x9mm, 0.5mm间距。这两种封装设计旨在满足不同空间和性能需求的嵌入式系统。应用领域广泛，包括但不限于物联网(IoT)设备、智能家居、工业自动化、车载信息娱乐系统、医疗设备和各种智能终端。i.MX6ULL的低功耗特性使其特别适合需要长时间工作的远程传感器和移动设备。数据手册还详细列出了订购代码，例如MCIMX6Y0CVM05AA、MCIMX6Y1CVM05AA等，这些代码用于区分不同的配置和版本，以满足不同客户的具体需求。 i.MX6ULL处理器是恩智浦针对工业级应用精心打造的一款解决方案，它的高性能、低功耗特性和丰富的内存接口使其成为各种连接设备的理想选择。通过深入理解和应用i.MX6ULL的数据手册，开发者能够充分利用该处理器的优势，设计出高效、可靠的系统。

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i.MX 6ULL Applications Processors for Industrial Products, Rev. 1.2, 11/2017

16 NXP Semiconductors

Modules List

TSC Touch Screen Touch Controller With touch controller to support 4-wire and 5-wire

resistive touch panel.

TZASC Trust-Zone Address

Space Controller

Security The TZASC (TZC-380 by Arm) provides security

address region control functions required for intended

application. It is used on the path to the DRAM

controller.

UART1

UART2

UART3

UART4

UART5

UART6

UART7

UART8

UART Interface Connectivity

Peripherals

Each of the UARTv2 module supports the following

serial data transmit/receive protocols and

configurations:

• 7- or 8-bit data words, 1 or 2 stop bits, programmable

parity (even, odd or none)

• Programmable baud rates up to 5 Mbps.

• 32-byte FIFO on Tx and 32 half-word FIFO on Rx

supporting auto-baud

uSDHC1

uSDHC2

SD/MMC and SDXC

Enhanced Multi-Media

Card / Secure Digital Host

Controller

Connectivity

Peripherals

i.MX 6ULL specific SoC characteristics:

All four MMC/SD/SDIO controller IPs are identical and

are based on the uSDHC IP. They are:

• Fully compliant with MMC command/response sets

and Physical Layer as defined in the Multimedia Card

System Specification, v4.5/4.2/4.3/4.4/4.41/

including high-capacity (size > 2 GB) cards HC MMC.

• Fully compliant with SD command/response sets

and Physical Layer as defined in the SD Memory

Card Specifications, v3.0 including high-capacity

SDXC cards up to 2 TB.

• Fully compliant with SDIO command/response sets

and interrupt/read-wait mode as defined in the SDIO

Card Specification, Part E1, v3.0

Two ports support:

• 1-bit or 4-bit transfer mode specifications for SD and

SDIO cards up to UHS-I SDR104 mode (104 MB/s

max)

• 1-bit, 4-bit, or 8-bit transfer mode specifications for

MMC cards up to 52 MHz in both SDR and DDR

modes (104 MB/s max)

• 4-bit or 8-bit transfer mode specifications for eMMC

chips up to 200 MHz in HS200 mode (200 MB/s max)

However, the SoC level integration and I/O muxing logic

restrict the functionality to the following:

• Instances #1 and #2 are primarily intended to serve

as interfaces to on-board peripherals. These ports

are equipped with “Card detection” and “Write

Protection” pads and do not support hardware reset.

• All ports can work with 1.8 V and 3.3 V cards. There

are two completely independent I/O power domains

for Ports #1 and #2 in four bit configuration (SD

interface).

Table 2. i.MX 6ULL Modules List (continued)

Block Mnemonic Block Name Subsystem Brief Description

i.MX 6ULL Applications Processors for Industrial Products, Rev. 1.2, 11/2017

18 NXP Semiconductors

Modules List

3.1 Special Signal Considerations

Table 3 lists special signal considerations for the i.MX 6ULL processors. The signal names are listed in

alphabetical order.

The package contact assignments can be found in Section 6, “Package Information and Contact

Assignments".” Signal descriptions are provided in the i.MX 6ULL Reference Manual (IMX6ULLRM).

Table 3. Special Signal Considerations

Signal Name Remarks

CCM_CLK1_P/

CCM_CLK1_N

One general purpose differential high speed clock Input/output is provided.

It can be used:

• To feed external reference clock to the PLLs and further to the modules inside SoC.

• To output internal SoC clock to be used outside the SoC as either reference clock or as a

functional clock for peripherals.

See the i.MX 6ULL Reference Manual (IMX6ULLRM) for details on the respective clock trees.

Alternatively one may use single ended signal to drive CLK1_P input. In this case corresponding

CLK1_N input should be tied to the constant voltage level equal 1/2 of the input signal swing.

Termination should be provided in case of high frequency signals.

After initialization, the CLK1 input/output can be disabled (if not used). If unused, either or both of

the CLK1_N/P pairs may remain unconnected.

RTC_XTALI/RTC_XTALO If the user wishes to configure RTC_XTALI and RTC_XTALO as an RTC oscillator, a 32.768 kHz

crystal, (100 k ESR, 10 pF load) should be connected between RTC_XTALI and RTC_XTALO.

Keep in mind the capacitors implemented on either side of the crystal are about twice the crystal

load capacitor. To hit the exact oscillation frequency, the board capacitors need to be reduced to

account for board and chip parasitics. The integrated oscillation amplifier is self biasing, but

relatively weak. Care must be taken to limit parasitic leakage from RTC_XTALI and RTC_XTALO

to either power or ground (>100 M). This will debias the amplifier and cause a reduction of startup

margin. Typically RTC_XTALI and RTC_XTALO should bias to approximately 0.5 V.

If it is desired to feed an external low frequency clock into RTC_XTALI the RTC_XTALO pin should

be remain unconnected or driven with a complimentary signal. The logic level of this forcing clock

should not exceed VDD_SNVS_CAP level and the frequency should be <100 kHz under typical

conditions.

In case when high accuracy real time clock are not required, system may use internal low

frequency ring oscillator. It is recommended to connect RTC_XTALI to GND and keep RTC_XTALO

unconnected.

XTALI/XTALO A 24.0 MHz crystal should be connected between XTALI and XTALO.

The crystal must be rated for a maximum drive level of 250 W. An ESR (equivalent series

resistance) of typical 80  is recommended. NXP BSP (board support package) software requires

24 MHz on XTALI/XTALO.

The crystal can be eliminated if an external 24 MHz oscillator is available in the system. In this

case, XTALO must be directly driven by the external oscillator and XTALI is disconnected.

If this clock is used as a reference for USB, then there are strict frequency tolerance and jitter

requirements. See OSC24M chapter and relevant interface specifications chapters for details.

DRAM_VREF When using DDR_VREF with DDR I/O, the nominal reference voltage must be half of the

NVCC_DRAM supply. The user must tie DDR_VREF to a precision external resistor divider. Use a

1k 0.5% resistor to GND and a 1 k 0.5% resistor to NVCC_DRAM. Shunt each resistor with a

closely-mounted 0.1 µF capacitor.

To reduce supply current, a pair of 1.5 k 0.1% resistors can be used. Using resistors with

recommended tolerances ensures the ± 2% DDR_VREF tolerance (per the DDR3 specification) is

maintained when two DDR3 ICs plus the i.MX 6ULL are drawing current on the resistor divider.

Modules List

i.MX 6ULL Applications Processors for Industrial Products, Rev. 1.2, 11/2017

NXP Semiconductors 19

3.2 Recommended Connections for Unused Analog Interfaces

Table 5 shows the recommended connections for unused analog interfaces.

ZQPAD DRAM calibration resistor 240  1% used as reference during DRAM output buffer driver

calibration should be connected between this pad and GND.

GPANAIO This signal is reserved for NXP manufacturing use only. This output must remain unconnected.

JTAG_nnnn The JTAG interface is summarized in Table 4. Use of external resistors is unnecessary. However,

if external resistors are used, the user must ensure that the on-chip pull-up/down configuration is

followed. For example, do not use an external pull down on an input that has on-chip pull-up.

JTAG_TDO is configured with a keeper circuit such that the non-connected condition is eliminated

if an external pull resistor is not present. An external pull resistor on JTAG_TDO is detrimental and

should be avoided.

JTAG_MOD is referenced as SJC_MOD in the i.MX 6ULL reference manual. Both names refer to

the same signal. JTAG_MOD must be externally connected to GND for normal operation.

Termination to GND through an external pull-down resistor (such as 1 k) is allowed. JTAG_MOD

set to hi configures the JTAG interface to mode compliant with IEEE1149.1 standard. JTAG_MOD

set to low configures the JTAG interface for common SW debug adding all the system TAPs to the

chain.

NC These signals are No Connect (NC) and should be disconnected by the user.

POR_B This cold reset negative logic input resets all modules and logic in the IC.

May be used in addition to internally generated power on reset signal (logical AND, both internal

and external signals are considered active low).

ONOFF ONOFF can be configured in debounce, off to on time, and max time-out configurations. The

debounce and off to on time configurations supports 0, 50, 100 and 500 ms. Debounce is used to

generate the power off interrupt. While in the ON state, if ONOFF button is pressed longer than the

debounce time, the power off interrupt is generated. Off to on time supports the time it takes to

request power on after a configured button press time has been reached. While in the OFF state,

if ONOFF button is pressed longer than the off to on time, the state will transition from OFF to ON.

Max time-out configuration supports 5, 10, 15 seconds and disable. Max time-out configuration

supports the time it takes to request power down after ONOFF button has been pressed for the

defined time.

TEST_MODE TEST_MODE is for NXP factory use. The user must tie this pin directly to GND.

Table 4. JTAG Controller Interface Summary

JTAG I/O Type On-chip Termination

JTAG_TCK Input 47 k

pull-up

JTAG_TMS Input 47 kpull-up

JTAG_TDI Input 47 kpull-up

JTAG_TDO 3-state output Keeper

JTAG_TRSTB Input 47 kpull-up

JTAG_MOD Input 100 kpull-up

Table 3. Special Signal Considerations (continued)

Signal Name Remarks

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