Cortex-A8技术手册：ARMv8架构详解

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本资源是ARM官方发布的Cortex-A8 Technical Reference Manual（Cortex-A8技术参考手册），版本为r3p2，涵盖了ARM Cortex-A8核心处理器的详细技术规格和信息。该手册由2006年至2010年期间更新，版权归ARM Limited所有，非公开资料。在Cortex-A8技术手册中，首先强调了版权信息，指出任何复制或改编必须事先获得ARM Limited的书面许可，以保护其知识产权。手册中的内容反映了ARM对于产品不断进行的改进和发展，旨在提供准确的产品特性描述。它可能包含以下关键知识点： 1. **架构概览**：作为ARM Cortex-A系列的一员，Cortex-A8是一款基于ARMv7架构的高性能应用级处理器，旨在为移动设备、嵌入式系统和服务器等应用提供出色的性能和能效。 2. **指令集与特性**：手册详细解释了Cortex-A8所采用的ARMv7指令集，包括Thumb-2双模式、超标量执行单元、硬件虚拟化支持、内存管理单元（MMU）等，以及针对多媒体处理（如NEON向量处理器）和多线程优化的特点。 3. **流水线设计**：手册深入探讨了Cortex-A8的前端和后端流水线，包括取指/解码、执行、存储器访问和写回等阶段，帮助开发者理解其性能瓶颈和优化策略。 4. **缓存体系**：介绍了L1和L2数据和指令缓存的配置、缓存策略以及一致性协议，这对于提高处理器的性能至关重要。 5. **电源管理和节能技术**：手册可能包含关于Cortex-A8的低功耗模式（如Cortex-MX系列中的LP和ULP模式）以及动态电压频率缩放（DVFS）的介绍，以适应不同应用场景下的能效需求。 6. **中断处理和异常管理**：描述了中断系统的工作原理、优先级管理、异常处理流程，以及与操作系统交互的方式。 7. **安全性**：如果手册包含这一部分，可能会涉及TrustZone安全架构，允许在硬件层面实现安全区域和隔离，保护敏感数据和执行环境。 8. **接口和总线规范**：讨论了Cortex-A8与其他外设（如内存控制器、总线接口、外设接口）的连接方式，以及相应的规范和接口标准。 9. **性能评估和基准测试**：手册可能提供了一些性能指标和推荐的最佳实践，以便开发者了解实际应用中的性能表现。 10. **软件开发和调试**：指导开发者如何编写兼容Cortex-A8架构的代码，以及使用调试工具进行有效调试。 Cortex-A8 Technical Reference Manual为工程师和开发者提供了深入了解这款处理器的全方位指南，无论是在设计、优化还是实现特定功能时，都是不可或缺的参考资料。

List of Figures

ID060510 Non-Confidential

Figure 3-17 Silicon ID Register format ......................................................................................................... 3-41

Figure 3-18 Cache Size Identification Register format ................................................................................. 3-42

Figure 3-19 Cache Size Selection Register format ...................................................................................... 3-43

Figure 3-20 Control Register bit assignments .............................................................................................. 3-45

Figure 3-21 Auxiliary Control Register format .............................................................................................. 3-48

Figure 3-22 Coprocessor Access Control Register format ........................................................................... 3-52

Figure 3-23 Secure Configuration Register format ....................................................................................... 3-53

Figure 3-24 Secure Debug Enable Register format ..................................................................................... 3-55

Figure 3-25 Nonsecure Access Control Register format .............................................................................. 3-56

Figure 3-26 Translation Table Base Register 0 format ................................................................................ 3-58

Figure 3-27 Translation Table Base Register 1 format ................................................................................ 3-59

Figure 3-28 Translation Table Base Control Register format ....................................................................... 3-61

Figure 3-29 Domain Access Control Register format ................................................................................... 3-62

Figure 3-30 Data Fault Status Register format ............................................................................................. 3-63

Figure 3-31 Instruction Fault Status Register format .................................................................................... 3-65

Figure 3-32 c7 format for set and way .......................................................................................................... 3-70

Figure 3-33 c7 format for MVA ..................................................................................................................... 3-71

Figure 3-34 PA Register format for successful translation ........................................................................... 3-71

Figure 3-35 PA Register format for unsuccessful translation ....................................................................... 3-72

Figure 3-36 TLB Operations MVA and ASID format .................................................................................... 3-76

Figure 3-37 TLB Operations ASID format .................................................................................................... 3-76

Figure 3-38 Performance Monitor Control Register format .......................................................................... 3-77

Figure 3-39 Count Enable Set Register format ............................................................................................ 3-78

Figure 3-40 Count Enable Clear Register format ......................................................................................... 3-79

Figure 3-41 FLAG Register format ............................................................................................................... 3-81

Figure 3-42 Software Increment Register format ......................................................................................... 3-82

Figure 3-43 Performance Counter Selection Register format ...................................................................... 3-83

Figure 3-44 Event Selection Register format ............................................................................................... 3-84

Figure 3-45 User Enable Register format ..................................................................................................... 3-89

Figure 3-46 Interrupt Enable Set Register format ........................................................................................ 3-90

Figure 3-47 Interrupt Enable Clear Register format ..................................................................................... 3-92

Figure 3-48 L2 Cache Lockdown Register format ........................................................................................ 3-93

Figure 3-49 L2 Cache Auxiliary Control Register format .............................................................................. 3-95

Figure 3-50 TLB Lockdown Register format ................................................................................................. 3-98

Figure 3-51 Primary Region Remap Register format ................................................................................. 3-101

Figure 3-52 Normal Memory Remap Register format ................................................................................

3-102

Figure 3-53 PLE Identification and Status Registers format ...................................................................... 3-105

Figure 3-54 PLE User Accessibility Register format .................................................................................. 3-106

Figure 3-55 PLE Channel Number Register format ................................................................................... 3-108

Figure 3-56 PLE Control Register format ................................................................................................... 3-110

Figure 3-57 PLE Internal Start Address Register bit format ....................................................................... 3-112

Figure 3-58 PLE Internal End Address Register format ............................................................................. 3-113

Figure 3-59 PLE Channel Status Register format ...................................................................................... 3-114

Figure 3-60 PLE Context ID Register format .............................................................................................. 3-116

Figure 3-61 Secure or Nonsecure Vector Base Address Register format .................................................. 3-117

Figure 3-62 Monitor Vector Base Address Register format ........................................................................ 3-118

Figure 3-63 Interrupt Status Register format .............................................................................................. 3-119

Figure 3-64 FCSE PID Register format ...................................................................................................... 3-121

Figure 3-65 Address mapping with the FCSE PID Register ....................................................................... 3-122

Figure 3-66 Context ID Register format ..................................................................................................... 3-122

Figure 3-67 Instruction and Data side Data 0 Registers format ................................................................. 3-125

Figure 3-68 Instruction and Data side Data 1 Registers format ................................................................. 3-125

Figure 3-69 L1 TLB CAM read operation format ........................................................................................ 3-129

Figure 3-70 L1 TLB CAM write operation format ........................................................................................ 3-129

Figure 3-71 L1 HVAB array read operation format ..................................................................................... 3-131

Figure 3-72 L1 HVAB array write operation format .................................................................................... 3-131

Figure 3-73 L1 tag array read operation format ......................................................................................... 3-132

Figure 3-74 L1 tag array write operation format ......................................................................................... 3-132

Figure 3-75 L1 data array read operation format ....................................................................................... 3-133

Figure 3-76 L1 data array write operation format ....................................................................................... 3-133

List of Figures

ID060510 Non-Confidential

Figure 3-77 BTB array read operation format ............................................................................................ 3-134

Figure 3-78 BTB array write operation format ............................................................................................ 3-135

Figure 3-79 GHB array read operation format ............................................................................................ 3-135

Figure 3-80 GHB array write operation format ........................................................................................... 3-136

Figure 3-81 L2 Data 0 Register format ....................................................................................................... 3-137

Figure 3-82 L2 Data 1 Register format ....................................................................................................... 3-137

Figure 3-83 L2 Data 2 Register format ....................................................................................................... 3-137

Figure 3-84 L2 parity/ECC array read operation format ............................................................................. 3-139

Figure 3-85 L2 parity/ECC array write operation format ............................................................................. 3-139

Figure 3-86 L2 tag array read operation format ......................................................................................... 3-140

Figure 3-87 L2 tag array write operation format ......................................................................................... 3-140

Figure 3-88 L2 data RAM array read operation format .............................................................................. 3-141

Figure 3-89 L2 data RAM array write operation format .............................................................................. 3-141

Figure 6-1 16MB supersection descriptor format ......................................................................................... 6-4

Figure 8-1 L2 cache bank structure .............................................................................................................. 8-3

Figure 10-1 CLK-to-ACLK ratio of 4:1 .......................................................................................................... 10-2

Figure 10-2 Changing the CLK-to-ACLK ratio from 4:1 to 1:1 ...................................................................... 10-3

Figure 10-3 Changing the PCLK-to-internal-PCLK ratio from 4:1 to 1:1 ...................................................... 10-3

Figure 10-4 Changing the ATCLK-to-internal-ATCLK ratio from 4:1 to 1:1 .................................................. 10-3

Figure 10-5 Power-on reset timing ............................................................................................................... 10-5

Figure 10-6 Soft reset timing ........................................................................................................................ 10-6

Figure 10-7 PRESETn and ATRESETn assertion ....................................................................................... 10-6

Figure 10-8 STANDBYWFI deassertion ....................................................................................................... 10-9

Figure 10-9 CLKSTOPREQ and CLKSTOPACK ......................................................................................... 10-9

Figure 10-10 Power domains ....................................................................................................................... 10-12

Figure 10-11 Voltage domains ..................................................................................................................... 10-14

Figure 10-12 Retention power domains ....................................................................................................... 10-21

Figure 11-1 L1 MBIST Instruction Register bit assignments ........................................................................ 11-3

Figure 11-2 L2 MBIST Instruction Register bit assignments .......................................................................

. 11-6

Figure 11-3 L1 and L2 MBIST GO-NOGO Instruction Registers bit assignments ..................................... 11-10

Figure 11-4 L1 MBIST GO-NOGO Instruction Register example with two patterns ................................... 11-11

Figure 11-5 L1 MBIST Datalog Register bit assignments .......................................................................... 11-11

Figure 11-6 L2 MBIST Datalog Register bit assignments .......................................................................... 11-12

Figure 11-7 Timing of MBIST instruction load ............................................................................................ 11-15

Figure 11-8 Timing of MBIST custom GO-NOGO instruction load ............................................................. 11-16

Figure 11-9 Timing of MBIST at-speed execution ...................................................................................... 11-16

Figure 11-10 Timing of MBIST end-of-test datalog retrieval ........................................................................ 11-17

Figure 11-11 Timing of MBIST start of bitmap datalog retrieval ................................................................... 11-17

Figure 11-12 Timing of MBIST end of bitmap datalog retrieval .................................................................... 11-18

Figure 11-13 Physical array after pass 1 of CKBD ....................................................................................... 11-20

Figure 11-14 Physical array after pass 1 of COLBAR .................................................................................. 11-21

Figure 11-15 Physical array after pass 1 of ROWBAR ................................................................................ 11-21

Figure 11-16 Row 1 column 2 state during pass 2 of RWXMARCH ............................................................ 11-22

Figure 11-17 Row 1 column 2 state during pass 2 of RWYMARCH ............................................................ 11-22

Figure 11-18 Row 1 column 2 state during pass 2 of RWRXMARCH .......................................................... 11-23

Figure 11-19 Row 1 column 2 state during pass 2 of RWRYMARCH .......................................................... 11-23

Figure 11-20 Row 1 column 2 state during pass 2 of XMARCHC ................................................................ 11-24

Figure 11-21 Row 1 column 2 state during pass 2 of YMARCHC ................................................................ 11-24

Figure 11-22 XADDRBAR array accessing and data ................................................................................... 11-25

Figure 11-23 YADDRBAR array accessing and data ................................................................................... 11-25

Figure 11-24 WRITEBANG .......................................................................................................................... 11-26

Figure 11-25 READBANG ............................................................................................................................ 11-26

Figure 11-26 Input wrapper boundary register cell control logic .................................................................. 11-28

Figure 11-27 Output wrapper boundary register cell control logic ................................................................ 11-29

Figure 11-28 IEEE 1500-compliant input wrapper boundary register cell .................................................... 11-29

Figure 11-29 Reset handling ........................................................................................................................ 11-30

Figure 11-30 Safe shift RAM signal ..............................................................................................

................ 11-30

Figure 12-1 Typical debug system ............................................................................................................... 12-2

Figure 12-2 Debug ID Register format ....................................................................................................... 12-13

Figure 12-3 Debug ROM Address Register format .................................................................................... 12-14

List of Figures

ID060510 Non-Confidential

Figure 12-4 Debug Self Address Offset Register format ............................................................................ 12-15

Figure 12-5 Debug Status and Control Register format ............................................................................. 12-16

Figure 12-6 DTR Register format ............................................................................................................... 12-21

Figure 12-7 Vector Catch Register format .................................................................................................. 12-22

Figure 12-8 Event Catch Register format ................................................................................................... 12-24

Figure 12-9 Debug State Cache Control Register format .......................................................................... 12-25

Figure 12-10 ITR format ............................................................................................................................... 12-25

Figure 12-11 Debug Run Control Register format ........................................................................................ 12-26

Figure 12-12 Breakpoint Control Registers format ....................................................................................... 12-27

Figure 12-13 Watchpoint Control Registers format ...................................................................................... 12-31

Figure 12-14 OS Lock Access Register format ............................................................................................ 12-33

Figure 12-15 OS Lock Status Register format ............................................................................................. 12-34

Figure 12-16 OS Save and Restore Register format ................................................................................... 12-34

Figure 12-17 PRCR format ........................................................................................................................... 12-36

Figure 12-18 PRSR format ........................................................................................................................... 12-37

Figure 12-19 Integration Internal Output Control Register format ................................................................ 12-40

Figure 12-20 Integration External Output Control Register format ............................................................... 12-41

Figure 12-21 Integration Input Status Register format ................................................................................. 12-42

Figure 12-22 Integration Mode Control Register format ............................................................................... 12-43

Figure 12-23 Claim Tag Set Register format ................................................................................................ 12-44

Figure 12-24 Claim Tag Clear Register format ............................................................................................ 12-44

Figure 12-25 Lock Access Register format .................................................................................................. 12-45

Figure 12-26 Lock Status Register format .................................................................................................... 12-45

Figure 12-27 Authentication Status Register format .................................................................................... 12-46

Figure 12-28 Device Type Register format .................................................................................................. 12-47

Figure 12-29 Timing of core power-down and power-up sequences ........................................................... 12-66

Figure 13-1 NEON and VFP register bank ................................................................................................... 13-3

Figure 13-2 Register banks .......................................................................................................................... 13-6

Figure 13-3 Floating-Point System ID Register format ............................................................................... 13-11

Figure 13-4 Floating-Point Status and Control Register format ................................................................. 13-12

Figure 13-5 Floating-Point Exception Register format ............................................................................... 13-14

Figure 13-6 MVFR0 Register format .......................................................................................................... 13-14

Figure 13-7 MVFR1 Register format .......................................................................................................... 13-15

Figure 14-1 Example CoreSight debug environment ................................................................................... 14-4

Figure 14-2 ID Register format ..................................................................................................

................... 14-7

Figure 14-3 Configuration Code Register format ......................................................................................... 14-8

Figure 14-4 Configuration Code Extension Register format ......................................................................... 14-9

Figure 14-5 Mapping between the Component ID Registers and the component ID value ....................... 14-11

Figure 14-6 ITMISCOUT Register format ................................................................................................... 14-12

Figure 14-7 ITMISCIN Register format ....................................................................................................... 14-13

Figure 14-8 ITTRIGGER Register format ................................................................................................... 14-13

Figure 14-9 ITATBDATA0 Register format ................................................................................................. 14-14

Figure 14-10 ITATBCTR2 Register format ................................................................................................... 14-14

Figure 14-11 ITATBCTR1 Register format ................................................................................................... 14-15

Figure 14-12 ITATBCTR0 Register format ................................................................................................... 14-15

Figure 15-1 Debug system components ...................................................................................................... 15-2

Figure 15-2 Cross Trigger Interface channels .............................................................................................. 15-3

Figure 15-3 Asynchronous to synchronous converter .................................................................................. 15-7

Figure 15-4 CTI Control Register format .................................................................................................... 15-11

Figure 15-5 CTI Interrupt Acknowledge Register format ............................................................................ 15-11

Figure 15-6 CTI Application Trigger Set Register format ........................................................................... 15-12

Figure 15-7 CTI Application Trigger Clear Register format ........................................................................ 15-13

Figure 15-8 CTI Application Pulse Register format .................................................................................... 15-13

Figure 15-9 CTI Trigger to Channel Enable Registers format .................................................................... 15-14

Figure 15-10 CTI Channel to Trigger Enable Registers format .................................................................... 15-14

Figure 15-11 CTI Trigger In Status Register format ..................................................................................... 15-15

Figure 15-12 CTI Trigger Out Status Register format .................................................................................. 15-15

Figure 15-13 CTI Channel In Status Register format ..............................................................................

..... 15-16

Figure 15-14 CTI Channel Gate Register format ......................................................................................... 15-17

Figure 15-15 ASIC Control Register format ................................................................................................. 15-17

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