RESEARCH ARTICLE
Copyright © 2015 American Scientific Publishers
All rights reserved
Printed in the United States of America
Journal of
Computational and Theoretical Nanoscience
Vol. 12, 1–10, 2015
Position-Based Promotion Policy for the
Last Level Cache
Manman Peng
∗
, Bin Yu, and Tingting Zhu
College of Computer Science and Electronic Engineering, Hunan University, Changsha, China
The last level cache plays an impor tant role in mitigating long latencies between processor and main
memory. Recent studies have shown that changing the re-reference (or reuse) prediction on cache
insertions can significantly improve cache performance for memory-intensive workloads. Unlike
least-recently-used (LRU) replacement policy, these policies make the prediction of the incoming
blocks more correctly and hence reduce the amount of time which the zero-reused blocks occupy.
As a result, the high locality blocks get more opportunity to reside in the cache. However these
policies make the same prediction on a cache hit. That is, on any cache hit, the block is promoted to
the head of the ordered chain. This can potentially degrade cache performance when a cache block
is re-referenced and then never reused again. We show that simple changes to the promotion policy
can significantly reduce cache misses for memor y-intensive workloads. We propose Position-based
Promotion Policy (PPP) that predicts the re-reference interval of the reuse block based on its posi-
tion in the Re-Reference Interval Prediction (RRIP) chain. When combined with RRIP, PPP takes
both recency and frequency information into consideration at the same time. PPP requires minor
hardware modification on the RRIP. Our evaluations show that it achieves a speedup of 0.74% over
the original RRIP, and they outperfor m LRU by 3.2% and 2.4% respectively.
Keywords: Last Level Cache, Insertion Policy, Promotion Policy, Less Reused Block, Locality.
1. INTRODUCTION
The growing performance gap between processors and
memory has long been a primary bottleneck fo r hig h-end
processors. The last level cache (LLC) in cache hierar-
chy plays an important role in mitigating the processor-
memory gap by exp loiting temporal and spatial locality.
For many years, the cache has been managed by the least-
recently-used (LRU) replacement policy and its approx-
imations. Recent studies, however, have shown that the
LRU rep lacement policy can still be improved for appli-
cations which have a working set larger than the cache
or have mixed re-references pattern.
1, 2
As a result, some
of the studies proposed novel ideas to address the prob-
lem by simply modifying the cache insertion policy of
LRU replacement policy. This paper further squeezes the
room for cache performance improvement by addressing
the limits of the prior work.
Re-Reference Interval Prediction (RRIP),
2
a recently-
pro-posed framework, have altered the description of the
LRU chain. Rather than representing recency, it treats
∗
Author to whom correspondence should be addressed.
LRU chain as RRIP chain that represents the predicted re-
reference order of cache blocks. Cache block at the head
or the tail of the RRIP chain is predicted to have a near-
immediate or distant re-reference interval respectively.
Using the RRIP framework, the commonly-used LRU
replacement policy predicts all incoming blocks to have a
near-immediate re-reference interval and makes the same
prediction on a cache hit. Recent studies
1, 2
have shown
that always predicting a near-immediate re-reference inter-
val is not robust across all access patterns which may
contain either near-immediate o r distant re-references or
both. These access patterns was usually found in the work-
loads that have a working set larger than the cache or
have frequent bursts of references to non temporal data.
For such workloads, LRU blindly inserts all the blocks at
the head of the RRIP chain. These blocks which have a
distant re-reference interval travel from the most-recently-
used (MRU) position to the LRU position without receiv-
ing any cache hits and pollute the active block in the cache,
resulting inefficient use of cache space.
Dynamic Re-Reference Interval Prediction (DRRIP)
2
addresses this problem by dynamically choosing between
the two techniques, Static Re-Reference Interval Prediction
J. Comput. Theor. Nanosci. 2015, Vol. 12, No. 10 1546-1955/2015/12/001/010 doi:10.1166/jctn.2015.4264 1