PN5180：全NFC前端，高性能、广泛兼容的IC产品

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PN5180-Datasheet.pdf是一个高度集成的高性能全NFC论坛兼容前端IC，用于13.56 MHz的非接触式通信。该前端IC采用了出色的调制和解调概念，完全集成了不同类型的非接触式通信方法和协议。作为市场上最好的全NFC前端，PN5180可以确保下一代NFC的移动电话的最大互操作性。针对销售终端应用的点进行了优化，实现了高功率NFC前端功能，允许在没有额外的外部活动组件的情况下实现RF电平的EMV符合性。其支持所有NFC论坛模式，是一个高性能的多协议全NFC前端芯片。

NXP Semiconductors

PN5180A0xx/C3,C4

High-performance multiprotocol full NFC frontend, supporting all NFC Forum modes

In addition, the host can set the device into standby based on the

TEMPSENS_ERROR_IRQ_STAT.

This feature is enabled by default. Only the interrupt can be enabled / disabled via the

IRQ_ENABLE register

11.2.2 Reset and start-up time

A constant low level of at least 10 μs at the RESET_N pin starts the internal reset

procedure.

When the PN5180 has finished the start_up, a IDLE_IRQ is raised and the IC is ready to

receive commands on the host interface.

11.2.3 Clock concept

The PN5180 is supplied by an 27.12 MHz crystal for operation. In addition, the internal

PLL uses an accurate external clock source of either 8, 12, 16, 24 MHz instead of the

crystal.

The clock applied to the PN5180 provides a time basis for the RF encoder and decoder.

The stability of the clock frequency, is an important factor for correct operation. To obtain

optimum performance, clock jitter must be reduced as much as possible. Optimum

performance is best achieved using the internal oscillator buffer with the recommended

circuitry.

In card emulation mode, the clock is also required.

If an external clock source of 27.12 MHz is used instead of a crystal, the clock signal

must be applied to pin CLK1. In this case, special care must be taken with the clock duty

cycle and clock jitter (see Table 141).

The crystal is a component which is impacting the overall performance of the system.

A high-quality component is recommended here. The resistor RD1 reduces the start-up

time of the crystal. A short start-up time is especially desired in case the Low-Power card

detection is used. The values of these resistors depend on the crystal which is used.

aaa-020196

CLK1 CLK2

CL1 CL1

crystal

PN5180

VSS

Figure 5. Connection of crystal

11.3 Timer and Interrupt system

Product data sheet Rev. 3.9 — 17 November 2021

COMPANY PUBLIC 16 / 160

NXP Semiconductors

PN5180A0xx/C3,C4

High-performance multiprotocol full NFC frontend, supporting all NFC Forum modes

11.3.1 General Purpose Timer

The Timers are used to measure certain intervals between certain configurable events of

the receiver, transmitter and other RF-events. The timer signals its expiration by raising a

flag and the value of the timer may be accessed via the register-set.

Three general-purpose timers T0, T1, and T2 running with the PN5180 clock with

several start conditions, stop conditions, time resolutions, and maximal timer periods are

implemented.

For automatic timeout handling during MIFARE Classic Authentication Timer2 is blocked

during this operation.

In case EMVCo EMD handling is enabled (EMD_CONTROL register (address 0028h), bit

EMD_ENABLE) Timer1 is automatically restarted when an EMD event occurs.

Timers T0 to T2 has a resolution of 20 bits and may be operated at clock frequencies

derived from the 13.56 MHz system clock. Several start events can be configured: start

now, start on external RF-field on/off and start on Rx (receive)/Tx (transmit) started/

ended. The timers allow reload of the counter value. At expiration of the timers, a flag is

raised and an IRQ is triggered.

The clock may be divided by a prescaler for frequencies of:

• 6.78 MHz

• 3.39 MHz

• 1.70 MHz

• 848 kHz

• 424 kHz

• 212 kHz

• 106 kHz

• 53 kHz

11.3.2 Interrupt System

11.3.2.1 IRQ PIN

The IRQ_ENABLE configures, which of the interrupts are routed to the IRQ pin of the

PN5180. All of the interrupts can be enabled and disabled independent from each other.

The IRQ on the pin can either be cleared by writing to the IRQ_CLEAR register or by

reading the IRQ_STATUS register (EEPROM configuration). If not all enabled IRQ’s are

cleared, the IRQ pin remains active.

The polarity of the external IRQ signal is configured by EEPROM in IRQ_PIN_CONFIG

(01Ah).

11.3.2.2 IRQ_STATUS Register

The IRQ_STATUS register contains the status flags. The status flags cannot be disabled.

Status Flag can either be cleared by writing to the IRQ_CLEAR register or when the

IRQ_STATUS register is read (EEPROM configuration)

The PN5180 indicates certain events by setting bits in the register

GENERAL_IRQ_STATUS and additionally, if activated, on the pin IRQ.

LPCD_IRQ, GENERAL_ERROR_IRQ and HV_ERROR_IRQ are non-maskable

interrupts.

Product data sheet Rev. 3.9 — 17 November 2021

COMPANY PUBLIC 17 / 160

NXP Semiconductors

PN5180A0xx/C3,C4

High-performance multiprotocol full NFC frontend, supporting all NFC Forum modes

11.4 SPI Host Interface

The following description of the SPI host interface is valid for the NFC operation mode.

The Secure Firmware Download mode uses a different physical host interface handling.

Details are described in chapter 12.

11.4.1 Physical Host Interface

The interface of the PN5180 to a host microcontroller is based on a SPI interface,

extended by signal line BUSY. The maximum SPI speed is 7 Mbit/s and fixed to CPOL

= 0 and CPHA = 0. Only a half-duplex data transfer is supported. There is no chaining

allowed, meaning that the whole instruction has to be sent or the whole receive buffer

has to be read out. The whole transmit buffer shall be written at once as well. No NSS

assertion is allowed during data transfer.

As the MISO line is per default high-ohmic in case of NSS high, an internal pull-up

resistor can be enabled via EEPROM.

The BUSY signal is used to indicate that the PN5180 is not able to send or receive data

over the SPI interface.

The host interface is designed to support the typical interface supply voltages of 1.8 V

and 3.3 V of CPUs. A dedicated supply input which defines the host interface supply

voltage independent from other supplies is available (PVDD). Only a voltage of 1.8 V or

3.3 V is supported, but no voltage in the range of 1.95 V to 2.7 V.

• Master In Slave Out (MISO)

The MISO line is configured as an output in a slave device. It is used to transfer data

from the slave to the master, with the most significant bit sent first. The MISO signal is

put into 3-state mode when NSS is high.

• Master Out Slave In (MOSI)

The MOSI line is configured as an input in a slave device. It is used to transfer data from

the master to a slave, with the most significant bit sent first.

• Serial Clock (SCK)

The serial clock is used to synchronize data movement both in and out of the device

through its MOSI and MISO lines.

• Not Slave Select (NSS)

The slave select input (NSS) line is used to select a slave device. It shall be set to low

before any data transaction starts and must stay low during the transaction.

• Busy

During frame reception, the BUSY line goes ACTIVE and goes to IDLE when

PN5180 is able to receive a new frame or data is available (depending if SET or

GET frame is issued). If there is a parameter error, the IRQ is set to ACTIVE and a

GENERAL_ERROR_IRQ is set.

Both master and slave devices must operate with the same timing. The master device

always places data on the MOSI line a half cycle before the clock edge SCK, in order for

the slave device to latch the data.

The BUSY line is used to indicate that the system is processing data and cannot receive

any data from a host. The system handles the busy signal different for normal mode and

debug mode (test bus enabled). In the sequence below, step 3 is optional for the normal

Product data sheet Rev. 3.9 — 17 November 2021

COMPANY PUBLIC 18 / 160

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