TI TLC2558/2554：12位4通道低功耗ADC数据手册与特性

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"TLC2558系列是TI公司生产的一款12位、4通道或8通道、低功耗的串行模拟-to-数字转换器（ADC），具有自动电源关闭功能，适用于各种需要高精度、高速采样的应用场景。" TLC2558系列ADC芯片是德州仪器（TI）推出的产品，主要特点包括： 1. **高速度**：最大吞吐率可达400KSPS（每秒400千样点），这使得它们在需要快速采样的系统中表现出色。 2. **内置参考电压**：TLC2558集成有内部参考电压源，同时支持外部参考电压输入，为用户提供灵活的选择，以适应不同的应用需求。 3. **8倍FIFO**：内部的FIFO（First In First Out）缓冲区有助于处理高速数据流，提高了系统处理能力，并降低了主处理器的负担。 4. **高精度**：其差分/积分非线性误差仅为±1 LSB，这意味着在转换过程中能保持较高的精度，对于信号处理至关重要。 5. **信号质量**：信号至噪声和失真比（SNDR）为69dB，无杂散动态范围（SFDR）达到75dB，这些指标表明在12kHz频率下，该ADC能够提供良好的信号质量。 6. **宽电源电压**：TLC2558工作于5V单电源，允许模拟输入电压范围从0V到电源电压，适合处理宽范围的输入信号。 7. **带宽**：在500kHz带宽下，TLC2558能处理高频信号，满足多种应用的需要。 8. **串行接口**：支持SPI和DSP兼容的串行接口，时钟速度可高达20MHz，方便与各种微控制器或数字信号处理器进行通信。 9. **控制方式**：硬件控制和可编程的采样周期，提供了灵活的系统设计选项。 10. **低功耗**：在5.5V电源下，外接参考电压时电流消耗为4mA，内部参考电压时为6mA。同时，提供了软件和硬件控制的电源关闭模式，以及自动电源关闭模式，待机状态下电流仅为1μA，大大节省了系统功耗。 11. **引脚配置**：芯片引脚包括数据输出（SDO）、数据输入（SDI）、时钟输入（SCLK）、结束转换/中断（EOC/(INT)）、电源（VCC）、通道选择引脚（A0-A4或A0-A7，取决于是4通道还是8通道版本）、片选（CS）、参考电压正负极（REFP, REFM）、采样频率选择（FS）、电源关闭（PWDN）、地线（GND）以及开始转换引脚（CSTART）等。 TLC2558系列ADC适用于需要高精度、高速度转换且对功耗有严格要求的应用场景，如音频处理、工业自动化、医疗设备、测试测量设备等。通过其丰富的特性集和灵活的配置，可以有效地集成到各种系统设计中，实现高效的数据采集和处理。

TLC2554, TLC2558

5-V, 12-BIT, 400 KSPS, 4/8 CHANNEL, LOW POWER,

SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO POWER DOWN

SLAS220A –JUNE 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

control and timing (continued)

configuration

Configuration data is stored in one 12-bit configuration register (CFR) (see Table 2 for CFR bit definitions). Once

configured after first power up, the information is retained in the H/W or S/W power-down state. When the device

is being configured, a write CFR cycle is issued by the host processor. This is a 16-bit write. If the SCLK stops

after the first 8 bits are entered, then the next eight bits can be taken after the SCLK is resumed. The status of

the CFR can be read with a read CFR command.

Table 2. TLC2554/TLC2558 Configuration Register (CFR) Bit Definitions

BIT DEFINITION

D(15–12) All zeros, nonprogrammable

D11 Reference select

0: External

1: Internal

D10 Output select

0: Unipolar straight binary

1: 2’s complement

D9 Sample period select

0: Short sampling 12 SCLKs (1x sampling time)

1: Long sampling 24 SCLKs (2x sampling time)

D8 Conversion clock source select

0: Conversion clock = SCLK

1: Conversion clock = SCLK/2

D7 Input select

0: Normal

1: Pseudo differential CH A2(2558) or CH A1 (2554) is the differential input

D(6,5) Conversion mode select

00: Single shot mode

01: Repeat mode

10: Sweep mode

11: Repeat sweep mode

D(4,3)

†

TLC2558 TLC2554

Sweep auto sequence select

00: 0–1–2–3–4–5–6–7

01: 0–2–4–6–0–2–4–6

10: 0–0–2–2–4–4–6–6

11: 0–2–0–2–0–2–0–2

Sweep auto sequence select

00: N/A

01: 0–1–2–3–0–1–2–3

10: 0–0–1–1–2–2–3–3

11: 0–1–0–1–0–1–0–1

D2 EOC/INT – pin function select

0: Pin used as INT

1: Pin used as EOC

D(1,0) FIFO trigger level (sweep sequence length)

00: Full (INT

generated after FIFO level 7 filled)

01: 3/4 (INT

generated after FIFO level 5 filled)

10: 1/2 (INT

generated after FIFO level 3 filled)

11: 1/4 (INT

generated after FIFO level 1 filled)

†

These bits only take effect in conversion modes 10 and 11.

sampling

The sampling period starts after the first 4 input data are shifted in if they are decoded as one of the conversion

commands. These are select analog input (channel 0 through 7) and select test (channel 1 through 3).

TLC2554, TLC2558

5-V, 12-BIT, 400 KSPS, 4/8 CHANNEL, LOW POWER,

SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO POWER DOWN

SLAS220A –JUNE 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

normal sampling

When the converter is using normal sampling, the sampling period is programmable. It can be 12 SCLKs (short

sampling) or 24 SCLKs (long sampling). Long sampling helps the input analog signal sampled to settle to 0.5

LSB accuracy when input source resistance is high.

extended sampling

An asynchronous (to the SCLK) signal, via dedicated hardware pin CSTART, can be used in order to have total

control of the sampling period and the start of a conversion. This is extended sampling. The falling edge of

CSTART

is the start of the sampling period. The rising edge of CSTART is the end of the sampling period and

the start of the conversion. This function is useful for an application that requires:

The use of an extended sampling period to accommodate different input source impedance.

The use of a faster I/O clock on the serial port but not enough sampling time is available due to the fixed

number of SCLKs. This could be due to a high input source impedance or due to higher MUX ON resistance

at lower supply voltage (refer to application information).

Once the conversion is complete, the processor can initiate a read cycle using either the read FIFO command

to read the conversion result or simply select the next channel number for conversion. Since the device has a

valid conversion result in the output buffer, the conversion result is simply presented at the serial data output.

TLC2554/TLC2558 conversion modes

The TLC2554 and TLC2558 have four different conversion modes (mode 00, 01, 10, 11). The operation of each

mode is slightly different, depending on how the converter performs the sampling and which host interface is

used. The trigger for a conversion can be an active CSTART

(extended sampling), CS (normal sampling, SPI

interface), or FS (normal sampling, TMS320 DSP interface). When FS is used as the trigger, CS

can be held

active, i.e. CS

does not need to be toggled through the trigger sequence. Different types of triggers should not

be mixed throughout the repeat and sweep operations. When CSTART

is used as the trigger, the conversion

starts on the rising edge of CSTART

. The minimum low time for CSTART is 800 ns. If an active CS or FS is used

as the trigger, the conversion is started after the 16th or 28th SCLK edge. Enough time (for conversion) should

be allowed between consecutive triggers so that no conversion is terminated prematurely.

one shot mode (mode 00)

One shot mode (mode 00) does not use the FIFO, and the EOC is generated as the conversion is in progress

(or INT

is generated after the conversion is done).

repeat mode (mode 01)

Repeat mode (mode 01) uses the FIFO. Once the programmed FIFO threshold is reached, the FIFO must be

read, or the data is lost and the sequence starts over again. This allows the host to set up the converter and

continue monitoring a fixed input and come back to get a set of samples when preferred. The first conversion

must start with a select command so an analog input channel can be selected.

sweep mode (mode 10)

Sweep mode (mode 10) also uses the FIFO. Once it is programmed in this mode, all of the channels listed in

the selected sweep sequence are visited in sequence. The results are converted and stored in the FIFO. This

sweep sequence may not be completed if the FIFO threshold is reached before the list is completed. This allows

the system designer to change the sweep sequence length. Once the FIFO has reached its programmed

threshold, an interrupt (INT

) is generated. The host must issue a read FIFO command to read and clear the FIFO

before the next sweep can start.

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