Spartan-3AN FPGA 内置闪存使用指南

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本指南是专为Spartan-3AN FPGA设计的应用程序提供支持，特别是那些在配置后需要从或写入系统闪存内存的数据操作。Spartan-3AN FPGA是一种先进的可编程逻辑器件，其In-System Flash技术允许用户在系统运行时进行程序更新和数据存储。UG333（版本2.1）发布于2009年1月15日，提供了详细的用户手册，涵盖了如何有效地与Xilinx硬件设备配合，利用这些功能进行设计开发。该文档的核心内容主要包括以下几个方面： 1. **概述**：文档的目标是帮助设计者了解如何在Spartan-3AN FPGA中实现In-System Flash的读写操作。这适用于那些依赖于闪存进行实时升级、配置更改或者存储关键数据的设计项目。 2. **权限和许可**：Xilinx明确了文档的使用条款，用户只能在获得书面许可的情况下复制、分发或使用这些资料，不得擅自通过任何形式（如电子、机械、影印等）进行传播。此外，Xilinx保留随时修改文档的权利，并不保证无误，也不承担因文档错误而产生的责任。 3. **技术支持和更新**：虽然文档包含了关于In-System Flash功能的信息，但用户应意识到Xilinx并不承诺提供技术支持或定期更新文档以反映最新的技术发展。 4. **操作指南**：指南详细解释了如何在设计过程中集成In-System Flash功能，包括但不限于初始化、数据传输协议、错误处理以及安全措施。设计者需要遵循指南中的步骤，确保操作的正确性和系统的稳定性。 5. **资源获取**：文档的访问可通过Xilinx官方网站www.xilinx.com获取，用户可以在那里找到最新版本和可能的补充材料。 Spartan-3AN FPGA In-System Flash User Guide是一份实用的工具，对于任何希望利用这种先进功能进行高效设计的工程师来说，它提供了不可或缺的技术指导。理解并遵循指南中的规则和操作流程，可以帮助设计师最大限度地发挥Spartan-3AN FPGA的潜力，同时避免潜在的问题和风险。

Spartan-3AN FPGA In-System Flash User Guide www.xilinx.com 15

UG333 (v2.1) January 15, 2009

Chapter 2

In-System Flash Memory Architecture

Block Diagram

The Spartan

-3AN FPGA In-System Flash (ISF) memory consists of a main nonvolatile,

reprogrammable Flash memory array and one or two SRAM page buffers, as shown in

Figure 2-1. The Flash memory array is organized into Pages, Blocks, and Sectors. The

smallest erasable unit is a Page. Page size depends on both the device and the addressing

mode. The one or two SRAM page buffers simplify system interfaces and data

programming. All Spartan-3AN FPGAs, except the XC3S50AN FPGA, have two SRAM

page buffers. The XC3S50AN FPGA has a single such buffer.

All accesses to the ISF from the FPGA application are through a four-wire SPI interface, as

described in “SPI_ACCESS Design Primitive,” page 9.

Flash Memory Array

For optimal flexibility, the In-System Flash (ISF) memory is divided into three levels of

granularity, as shown in Figure 2-2. Figure 2-2 shows a specific example for the

XC3S700AN. Other Spartan-3AN FPGA family members are similar but either have a

different number of sectors or a different page size. The number of sectors and page size for

other Spartan-3AN FPGAs is listed in Table 2-1, page 16.

Figure 2-1: Internal SPI Flash Block Diagram

MOSI

MISO

Page

Flash Memory Array

SRAM Page Buffers

SPI_ACCESS

Page

CSB

CLK

Page Size

264/256 bytes: All but XC3S1400A

528/512 bytes: XC3S1400A

UG333_c1_01_020507

Buffer 1

Buffer 2

Buffer 2 available in all Spartan-3AN

FPGAs except the XC3S50AN

16 www.xilinx.com Spartan-3AN FPGA In-System Flash User Guide

UG333 (v2.1) January 15, 2009

Chapter 2: In-System Flash Memory Architecture

The most basic construct within the hierarchy is a memory Page. By default, a Page consists

of 264 bytes, except on the XC3S1400AN FPGA, which has a larger page size of 528 bytes.

The page size is reduced when the Optional Power-of-2 Addressing Mode is selected, as

shown in gray in Figure 2-2. The SRAM page buffer(s), shown in Figure 2-1, are large

enough to hold an entire page image. A page is the smallest erasable element within the

ISF memory, while a byte is the smallest readable and writable element within an SRAM

page buffer.

Pages are also grouped into a larger structure called a Block, which consists of 8 pages. The

Block Erase command provides an intermediate solution between the fast-but-small Page

Erase command and the slower-but-larger Sector Erase command.Finally, pages and

blocks are further combined into Sectors. A sector typically consists of 256 contiguous

pages or 32 contiguous blocks, except on the XC3S50AN, which has 128 pages per sector.

Sectors have additional control options. Sectors can be selectively write-protected by the

FPGA application, a featured called Sector Protection. Similarly, sectors can be

permanently locked down, preventing the contents from ever being erased or modified,

using a feature called Sector Lockdown. The sector controls similarly affect any data bytes,

pages, and blocks within the sector.

The ISF memory hierarchy directly impacts the ISF commands and addressing, as

described in subsequent sections.

Figure 2-2: XC3S700AN Internal SPI Flash Memory Hierarchy

Table 2-1: Spartan-3AN FPGA Memory Architecture

Device

Total Flash

Bits Sectors Sector Size

Pages per

Sector

Total

Pages

Page Size

(Bytes)

XC3S50AN 1,081,344 4 33K 128 512 264

XC3S200AN 4,325,376 8 66K

256

2,048 264

XC3S400AN 4,325,376 8 66K 2,048 264

XC3S700AN 8,650,752 16 66K 4,096 264

XC3S1400AN 17,301,504 16 132K 4,096 528

Page

264 bytes

(256 bytes)

Page 0

Page 1

Page 2

Page 3

Page 4

Page 5

Page 6

Page 7

Block = 8 Pages

Sector 2

Sector 3

Sector 15

Sector = 256 Pages

Sector 0

Sector 1

Sectors

Block = 2,112 bytes

(Block = 2,048 bytes)

= 32 Blocks

UG333_c2_01_092106

Spartan-3AN FPGA In-System Flash User Guide www.xilinx.com 17

UG333 (v2.1) January 15, 2009

Addressing Overview

Sector 0 is further subdivided into two, individually protected sub-sectors, as shown in

Figure 2-3. While the combined Sector 0 is the same size as all other sectors, Sector 0a is

always 8 pages while Sector 0b represents the remaining pages in Sector 0. Consequently,

the commands that operate on Sector 0 require slightly different addressing and control

than the same commands used on other sectors.

Spartan-3AN FPGA applications generally never make use of the split Sector 0 structure,

but applications must be aware that it exists in order to erase or protect Sector 0.

Addressing Overview

All commands that require an address use a 24-bit address field to select a sector, a block,

a page, or a byte location within a page. However, the In-System Flash memory supports

two different possible addressing schemes.

Addressing Modes

• All Spartan-3AN FPGAs, as delivered, use the Default Addressing Mode, detailed in

Table 2-2. All Xilinx® software primarily supports this mode.

• With an additional, special programming step, described in Appendix A, “Optional

Power-of-2 Addressing Mode”, Spartan-3AN FPGAs support a slightly different

addressing mode, which may be more natural for some applications.

The Default Addressing Mode provides roughly 3% more total memory bits. Figure 2-4,

page 18 shows the Flash memory array for the XC3S700AN FPGA, plus a detailed,

expanded diagram of a page within the Flash array. The diagram also describes how the 24

bits in a command address field select a sector, block, page, or byte within a memory page.

Figure 2-5 is a similar diagram specific to the XC3S1400AN, which uses a larger page size.

Using the Default Addressing Mode, each memory page is slightly larger than the typical

power-of-2 page size found in other memories. For example, all Spartan-3AN FPGAs

except the XC3S1400AN use a 264-byte page, while the XC3S1400AN memory pages are

double the size at 528 bytes. The “extra” bits are useful for a variety of applications.

• More total nonvolatile memory for FPGA configuration or data storage applications.

• Page pointers, linked address pointers, attributes, and status indicators for a Flash-

based file system.

• Error detection/correction bits for extreme applications.

Figure 2-3: Sector 0 is Sub-divided into Two Smaller Sub-sectors

Sector 0a

(8 pages )

Sector 0b

3S50AN: (120 pages)

All Other Sectors

UG333_c2_03_022607

Others: (248 pages)

3S50AN: (128 pages)

Others: (256 pages)

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