DDR SDRAM 256Mbits规格与技术详解（Elpida EDD2508A/EDD2516A）

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本文档是一份关于256Mbit DDR SDRAM（EDD2508AETA和EDD2516AETA）的技术数据表，由Elpida Memory公司发布，适用于2007年9月，主要针对开发工程师进行技术交流和分享。DDR SDRAM是一种高速内存技术，每时钟周期传输两次数据，支持双倍数据速率，提供了8Mwords×8bits×4banks或4Mwords×16bits×4banks的不同组织方式，适应了不同应用需求。文档中详细列出了以下关键参数： 1. **密度**: 256Mbits，即256兆位，存储容量大，适用于高数据密集型应用。 2. **组织结构**: - EDD2508AETA：8Mwords×8bits每个银行，共4个银行，支持连续和交错模式的突发长度2、4、8。 - EDD2516AETA：4Mwords×16bits每个银行，同样有4个银行。 3. **封装**：66-pin塑料TSOP（II）封装，符合RoHS无铅环保标准。 4. **电源供应**： - DDR400：工作电压VDD和VDDQ范围为2.6V±0.1V。 - DDR333和DDR266：VDD和VDDQ为2.5V±0.2V，支持不同速度等级。 5. **数据速率**：最高可达400Mbps/333Mbps/266Mbps。 6. **接口**：采用SSTL_2接口，保证高速数据传输。 7. **延迟时间**： - /CAS Latency (CL)：支持2个、2.5个或3个时钟周期的延迟，提高响应速度。 8. **预充电**：自动预充电选项，确保每次访问前数据线准备就绪。 9. **驱动强度**：提供正常和弱驱动选项以适应不同负载。 10. **刷新机制**：支持自动刷新和自刷新模式，保持数据在非活动期间保持稳定。 11. **刷新周期**：8192个周期/64毫秒，平均刷新周期为7.8微秒。 12. **工作温度范围**：0°C到+70°C，确保在各种环境下的可靠运行。该文档提供的信息有助于理解DDR SDRAM的工作原理、性能规格和操作特性，对设计和优化现代电子系统中的内存子系统具有重要价值。开发工程师可以借此了解如何选择合适的内存模块以及如何在系统设计中充分利用这些高级功能。

EDD2508AETA, EDD2516AETA

Data Sheet E0859E50 (Ver. 5.0)

AC Characteristics (TA = 0°C to +70°C, VDD, VDDQ = 2.5V ± 0.2V, VSS, VSSQ = 0V) [DDR333, 266]

-6B -7A -7B

Parameter Symbol

min. max. min. max min. max.

Unit Notes

Clock cycle time

(CL = 2)

tCK 7.5 12 7.5 12 10 12 ns 10

(CL = 2.5) tCK 6 12 7.5 12 7.5 12 ns

CK high-level width tCH 0.45 0.55 0.45 0.55 0.45 0.55 tCK

CK low-level width tCL 0.45 0.55 0.45 0.55 0.45 0.55 tCK

CK half period tHP

min

(tCH, tCL)

—

min

(tCH, tCL)

—

min

(tCH, tCL)

— tCK

DQ output access time from CK, /CK tAC –0.7 0.7 –0.75 0.75 –0.75 0.75 ns 2, 11

DQS output access time from CK,

/CK

tDQSCK –0.6 0.6 –0.75 0.75 –0.75 0.75 ns 2, 11

DQS to DQ skew tDQSQ — 0.45 — 0.5 — 0.5 ns 3

DQ/DQS output hold time from DQS tQH tHP – tQHS — tHP – tQHS — tHP – tQHS — ns

Data hold skew factor tQHS — 0.55 — 0.75 — 0.75 ns

Data-out high-impedance time from

CK, /CK

tHZ — 0.7 — 0.75 — 0.75 ns 5, 11

Data-out low-impedance time from

CK, /CK

tLZ –0.7 0.7 –0.75 0.75 –0.75 0.75 ns 6, 11

Read preamble tRPRE 0.9 1.1 0.9 1.1 0.9 1.1 tCK

Read postamble tRPST 0.4 0.6 0.4 0.6 0.4 0.6 tCK

DQ and DM input setup time tDS 0.45 — 0.5 — 0.5 — ns 8

DQ and DM input hold time tDH 0.45 — 0.5 — 0.5 — ns 8

DQ and DM input pulse width tDIPW 1.75 — 1.75 — 1.75 — ns 7

Write preamble setup time tWPRES 0 — 0 — 0 — ns

Write preamble tWPRE 0.25 — 0.25 — 0.25 — tCK

Write postamble tWPST 0.4 0.6 0.4 0.6 0.4 0.6 tCK 9

Write command to first DQS latching

transition

tDQSS 0.75 1.25 0.75 1.25 0.75 1.25 tCK

DQS falling edge to CK setup time tDSS 0.2 — 0.2 — 0.2 — tCK

DQS falling edge hold time from CK tDSH 0.2 — 0.2 — 0.2 — tCK

DQS input high pulse width tDQSH 0.35 — 0.35 — 0.35 — tCK

DQS input low pulse width tDQSL 0.35 0.35 — 0.35 — tCK

Address and control input setup time tIS 0.75 — 0.9 — 0.9 — ns 8

Address and control input hold time tIH 0.75 — 0.9 — 0.9 — ns 8

Address and control input pulse

width

tIPW 2.2 — 2.2 — 2.2 — ns 7

Mode register set command cycle

time

tMRD 2 — 2 — 2 — tCK

Active to Precharge command period tRAS 42 120000 45 120000 45 120000 ns

Active to Active/Auto-refresh

command period

tRC 60 — 65 — 65 — ns

Auto-refresh to Active/Auto-refresh

command period

tRFC 72 — 75 — 75 — ns

Active to Read/Write delay tRCD 18 — 20 — 20 — ns

Precharge to active command period tRP 18 — 20 — 20 — ns

Active to Autoprecharge delay tRAP tRCD min. — tRCD min. — tRCD min. — ns

Active to active command period tRRD 12 — 15 — 15 — ns

EDD2508AETA, EDD2516AETA

Data Sheet E0859E50 (Ver. 5.0)

-6B -7A -7B

Parameter Symbol

min. max. min. max min. max.

Unit Notes

Write recovery time tWR 15 — 15 — 15 — ns

Auto precharge write recovery and

precharge time

tDAL

(tWR/tCK)+

(tRP/tCK)

(tWR/tCK)+

(tRP/tCK)

—

(tWR/tCK)+

(tRP/tCK)

— tCK 13

Internal write to Read command

delay

tWTR 1 — 1 — 1 — tCK

Average periodic refresh interval tREF — 7.8 — 7.8 — 7.8 µs

Notes: 1. On all AC measurements, we assume the test conditions shown in the next page. For timing parameter

definitions, see ‘Timing Waveforms’ section.

2. This parameter defines the signal transition delay from the cross point of CK and /CK. The signal

transition is defined to occur when the signal level crossing VTT.

3. The timing reference level is VTT.

4. Output valid window is defined to be the period between two successive transition of data out or DQS

(read) signals. The signal transition is defined to occur when the signal level crossing VTT.

5. tHZ is defined as DOUT transition delay from Low-Z to High-Z at the end of read burst operation. The

timing reference is cross point of CK and /CK. This parameter is not referred to a specific DOUT voltage

level, but specify when the device output stops driving.

6. tLZ is defined as DOUT transition delay from High-Z to Low-Z at the beginning of read operation. This

parameter is not referred to a specific DOUT voltage level, but specify when the device output begins

driving.

7. Input valid windows is defined to be the period between two successive transition of data input or DQS

(write) signals. The signal transition is defined to occur when the signal level crossing VREF.

8. The timing reference level is VREF.

9. The transition from Low-Z to High-Z is defined to occur when the device output stops driving. A specific

reference voltage to judge this transition is not given.

10. tCK (max.) is determined by the lock range of the DLL. Beyond this lock range, the DLL operation is not

assured.

11. tCK = tCK (min) when these parameters are measured. Otherwise, absolute minimum values of these

values are 10% of tCK.

12. VDD is assumed to be 2.6V ± 0.1V (DDR400), 2.5V ± 0.2V (DDR333, 266). VDD power supply variation

per cycle expected to be less than 0.4V/400 cycle.

13. tDAL = (tWR/tCK)+(tRP/tCK)

For each of the terms above, if not already an integer, round to the next highest integer.

Example: For –5C Speed at CL = 3, tCK = 5ns, tWR = 15ns and tRP= 18ns,

tDAL = (15ns/5ns) + (18ns/5ns) = (3) + (4)

tDAL = 7 clocks

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