I2C总线规范与用户手册v7：高效IC间通信技术详解

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I2C-bus specification and user manual 7.0 是由Philips Semiconductors（现名为NXP Semiconductors）开发的一种简单易用的两点式双向总线系统，专为芯片间的高效控制设计，也被称为Inter-IC或I2C-bus。该手册详细介绍了I2C协议的不同模式，包括标准模式（Standard-mode）、快速模式（Fast-mode）、快速模式增强版（Fast-mode Plus, Fm+）和高速模式（High-speed），这些模式支持的数据传输速率分别高达100 kbit/s、400 kbit/s、1 Mbit/s 和 3.4 Mbit/s。在最高级别的UltraFast模式下，数据传输是单向的，可以达到5 Mbit/s的速率。核心知识点包括： 1. **I2C协议**：这是一种用于设备间通信的工业标准接口，采用两条信号线——串行数据线(SDA)和串行时钟线(SCL)，实现了低引脚数、低成本和易于扩展的通信方式。 2. **模式分类**： - **标准模式 (Standard-mode)**：基础的I2C通信，数据传输速率为100 kbit/s，适合低速、简单应用。 - **快速模式 (Fast-mode)**：提升数据传输速度至400 kbit/s，适合对速度有一定要求的应用。 - **快速模式增强版 (Fast-mode Plus, Fm+)**：进一步提高到1 Mbit/s，增加了错误检测能力。 - **高速模式 (High-speed, Hs)**：提供更高的数据传输速率，可达3.4 Mbit/s，适用于对速度有高需求的场合。 - **UltraFast模式 (UltraFast-mode, Ufm)**：专为单向数据传输设计，速度可达5 Mbit/s，适合特定的高速应用。 3. **术语变更**：手册更新了术语，将“master/slave”更改为“controller/target”，以符合MIPI IIc规范和NXP的包容性语言项目，强调了总线中的控制方和目标方角色。 4. **文档版本与更新**：这是一份用户手册的第七版，包含了对表格5的更新、术语调整以及新增的第9部分，反映了不断优化的技术支持和规范一致性。 5. **适用范围**：这份手册是为I2C设备开发者、工程师和维护人员设计的，提供了关于I2C-bus的设计、配置、测试和故障排查等实用指导。通过阅读这份手册，用户能够深入了解如何利用I2C协议进行高效、可靠的设备间通信，以及不同模式的选择和应用场景。

NXP Semiconductors

UM10204

C-bus specification and user manual

CLK

SCL

counter

reset

wait

state

start counting

HIGH period

mbc632

Figure 7. Clock synchronization during the arbitration procedure

When all controllers concerned have counted off their LOW period, the clock line is

released and goes HIGH. There is then no difference between the controller clocks and

the state of the SCL line, and all the controllers start counting their HIGH periods. The

first controller to complete its HIGH period pulls the SCL line LOW again.

In this way, a synchronized SCL clock is generated with its LOW period determined by

the controller with the longest clock LOW period, and its HIGH period determined by the

one with the shortest clock HIGH period.

3.1.8 Arbitration

Arbitration, like synchronization, refers to a portion of the protocol required only if more

than one controller is used in the system. Targets are not involved in the arbitration

procedure. A controller may start a transfer only if the bus is free. Two controllers may

generate a START condition within the minimum hold time (t

HD;STA

) of the START

condition which results in a valid START condition on the bus. Arbitration is then required

to determine which controller will complete its transmission.

Arbitration proceeds bit by bit. During every bit, while SCL is HIGH, each controller

checks to see if the SDA level matches what it has sent. This process may take many

bits. Two controllers can actually complete an entire transaction without error, as long

as the transmissions are identical. The first time a controller tries to send a HIGH, but

detects that the SDA level is LOW, the controller knows that it has lost the arbitration and

turns off its SDA output driver. The other controller goes on to complete its transaction.

No information is lost during the arbitration process. A controller that loses the arbitration

can generate clock pulses until the end of the byte in which it loses the arbitration and

must restart its transaction when the bus is free.

If a controller also incorporates a target function and it loses arbitration during the

addressing stage, it is possible that the winning controller is trying to address it. The

losing controller must therefore switch over immediately to its target mode.

Figure 8 shows the arbitration procedure for two controllers. More may be involved

depending on how many controllers are connected to the bus. The moment there is a

difference between the internal data level of the controller generating DATA1 and the

actual level on the SDA line, the DATA1 output is switched off. This does not affect the

data transfer initiated by the winning controller.

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NXP Semiconductors

UM10204

C-bus specification and user manual

msc609

DATA 1

DATA 2

SDA

SCL

controller 1 loses arbitration

DATA 1 SDA

Figure 8. Arbitration procedure of two controllers

Since control of the I

C-bus is decided solely on the address and data sent by competing

controllers, there is no central controller, nor any order of priority on the bus.

There is an undefined condition if the arbitration procedure is still in progress at the

moment when one controller sends a repeated START or a STOP condition while the

other controller is still sending data. In other words, the following combinations result in

an undefined condition:

• Controller 1 sends a repeated START condition and controller 2 sends a data bit.

• Controller 1 sends a STOP condition and controller 2 sends a data bit.

• Controller 1 sends a repeated START condition and controller 2 sends a STOP

condition.

3.1.9 Clock stretching

Clock stretching pauses a transaction by holding the SCL line LOW. The transaction

cannot continue until the line is released HIGH again. Clock stretching is optional and in

fact, most target devices do not include an SCL driver so they are unable to stretch the

clock.

On the byte level, a device may be able to receive bytes of data at a fast rate, but needs

more time to store a received byte or prepare another byte to be transmitted. Targets can

then hold the SCL line LOW after reception and acknowledgment of a byte to force the

controller into a wait state until the target is ready for the next byte transfer in a type of

handshake procedure (see Figure 7).

On the bit level, a device such as a microcontroller with or without limited hardware for

the I

C-bus, can slow down the bus clock by extending each clock LOW period. The

speed of any controller is adapted to the internal operating rate of this device.

In Hs-mode, this handshake feature can only be used on byte level (see Section 5.3.2).

3.1.10 The target address and R/W bit

Data transfers follow the format shown in Figure 9. After the START condition (S), a

target address is sent. This address is seven bits long followed by an eighth bit which is

a data direction bit (R/W) — a ‘zero’ indicates a transmission (WRITE), a ‘one’ indicates

a request for data (READ) (refer to Figure 10). A data transfer is always terminated by

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NXP Semiconductors

UM10204

C-bus specification and user manual

a STOP condition (P) generated by the controller. However, if a controller still wishes to

communicate on the bus, it can generate a repeated START condition (Sr) and address

another target without first generating a STOP condition. Various combinations of read/

write formats are then possible within such a transfer.

1 - 7 8 9 1 - 7 8 9 1 - 7 8 9

STOP

condition

START

condition

DATA ACKDATA ACKADDRESS ACKR/W

SDA

SCL

mbc604

Figure 9. A complete data transfer

mbc608

R/W

LSBMSB

target address

Figure 10. The first byte after the START procedure

Possible data transfer formats are:

• Controller-transmitter transmits to target-receiver. The transfer direction is not changed

(see Figure 11). The target receiver acknowledges each byte.

• Controller reads target immediately after first byte (see Figure 12). At the moment of

the first acknowledge, the controller-transmitter becomes a controller-receiver and the

target-receiver becomes a target-transmitter. This first acknowledge is still generated

by the target. The controller generates subsequent acknowledges. The STOP condition

is generated by the controller, which sends a not-acknowledge (A) just before the

STOP condition.

• Combined format (see Figure 13). During a change of direction within a transfer,

the START condition and the target address are both repeated, but with the R/W bit

reversed. If a controller-receiver sends a repeated START condition, it sends a not-

acknowledge (A) just before the repeated START condition.

Notes:

1. Combined formats can be used, for example, to control a serial memory. The internal

memory location must be written during the first data byte. After the START condition

and target address is repeated, data can be transferred.

2. All decisions on auto-increment or decrement of previously accessed memory

locations, etc., are taken by the designer of the device.

3. Each byte is followed by an acknowledgment bit as indicated by the A or A blocks in

the sequence.

4. I

C-bus compatible devices must reset their bus logic on receipt of a START or

repeated START condition such that they all anticipate the sending of a target

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