"TI TCA9554A I/O 扩展器：灵活的I/O 扩展解决方案"
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更新于2024-03-16
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The TI-TCA9554A is an I/O expander that allows for easy expansion of input and output capabilities for devices connected via the I2C or SMBus interface. It is designed to be controlled by a master device, such as a processor, through the SDA and SCL communication lines. The TCA9554A features 8 bidirectional I/O pins (P0-P7) that can be used for a variety of purposes, such as controlling LEDs, reading switch inputs, or driving status outputs.
The device is powered by VCC and ground connections, with additional control inputs such as ENABLE that can be used to enable or disable the I/O pins. The TCA9554A also features a RESET pin that can be used to reset the device to its default state. Additionally, the device includes an interrupt pin (INT) that can be used to signal the master device of an event or status change.
Overall, the TI-TCA9554A is a versatile and easy-to-use I/O expander that can greatly expand the capabilities of a master device. It is ideal for applications where additional I/O pins are needed, such as in industrial automation, robotics, or consumer electronics. With its compact size and simple interfacing, the TCA9554A is a valuable tool for enhancing the functionality of a wide range of devices.
8
TCA9554A
ZHCSDP5E –DECEMBER 2010–REVISED FEBRUARY 2017
www.ti.com.cn
Copyright © 2010–2017, Texas Instruments Incorporated
6.6 I
2
C Interface Timing Requirements
over operating free-air temperature range (unless otherwise noted) (see Figure 11)
MIN MAX UNIT
STANDARD MODE
f
scl
I
2
C clock frequency
0 100 kHz
t
sch
I
2
C clock high time
4 µs
t
scl
I
2
C clock low time
4.7 µs
t
sp
I
2
C spike time
50 ns
t
sds
I
2
C serial-data setup time
250 ns
t
sdh
I
2
C serial-data hold time
0 ns
t
icr
I
2
C input rise time
1000 ns
t
icf
I
2
C input fall time
300 ns
t
ocf
I
2
C output fall time
10-pF to 400-pF bus 300 ns
t
buf
I
2
C bus free time between Stop and Start
4.7 µs
t
sts
I
2
C Start or repeated Start condition setup
4.7 µs
t
sth
I
2
C Start or repeated Start condition hold
4 µs
t
sps
I
2
C Stop condition setup
4 µs
t
vd(data)
Valid data time SCL low to SDA output valid 3.45 ns
t
vd(ack)
Valid data time of ACK
condition
ACK signal from SCL low to
SDA (out) low
3.45 µs
C
b
I
2
C bus capacitive load
400 pF
FAST MODE
f
scl
I
2
C clock frequency
0 400 kHz
t
sch
I
2
C clock high time
0.6 µs
t
scl
I
2
C clock low time
1.3 µs
t
sp
I
2
C spike time
50 ns
t
sds
I
2
C serial-data setup time
100 ns
t
sdh
I
2
C serial-data hold time
0 ns
t
icr
I
2
C input rise time
20 300 ns
t
icf
I
2
C input fall time
20 × (V
DD
/ 5.5
V)
300 ns
t
ocf
I
2
C output fall time
10-pF to 400-pF bus
20 × (V
DD
/ 5.5
V)
300 ns
t
buf
I
2
C bus free time between Stop and Start
1.3 µs
t
sts
I
2
C Start or repeated Start condition setup
0.6 µs
t
sth
I
2
C Start or repeated Start condition hold
0.6 µs
t
sps
I
2
C Stop condition setup
0.6 µs
t
vd(data)
Valid data time SCL low to SDA output valid 0.9 ns
t
vd(ack)
Valid data time of ACK
condition
ACK signal from SCL low to
SDA (out) low
0.9 µs
C
b
I
2
C bus capacitive load
400 pF
6.7 Switching Characteristics
over operating free-air temperature range (unless otherwise noted) (see Figure 12 and Figure 13)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
MIN MAX UNIT
STANDARD MODE and FAST MODE
t
iv
Interrupt valid time P port INT 4 µs
t
ir
Interrupt reset delay time SCL INT 4 µs
t
pv
Output data valid SCL P7–P0 350 ns
t
ps
Input data setup time P port SCL 100 ns
t
ph
Input data hold time P port SCL 1 μs
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