Intel 386SX 数据手册：硬件开发的重要参考资料

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“Intel 386SX的Datasheet提供了关于这款处理器的详细技术规格和功能特性，是硬件开发者的重要参考资料。” Intel 386SX是一款由Intel公司推出的微处理器，它是80386系列的一个变种，主要针对那些需要32位处理能力但又受限于16位硬件环境的市场。这个处理器的设计旨在提供与标准32位Intel 386DX处理器相似的功能，但以更经济的成本实现。 386SX的核心特性包括： 1. **全32位内部架构**：尽管386SX被设计用于16位系统，但它具有完整的32位内部数据路径，这意味着它可以高效地处理32位数据类型。 2. **8-、16-、32位数据类型支持**：这使得386SX能够灵活处理不同宽度的数据，适应各种计算任务。 3. **8个通用32位寄存器**：这些寄存器增强了处理器的计算能力，使其能同时处理多个复杂操作。 4. **兼容性**：386SX运行Intel 386TM软件，且与8086、80186、80286以及386DX处理器的机器代码兼容。这意味着开发者可以使用相同的操作系统和应用程序，无需进行大规模的代码修改。 5. **高性能16位数据总线**：支持16、20、25和33MHz的时钟频率，以及两时钟周期的总线循环，提高了数据传输速率。 6. **地址流水线技术**：通过地址流水线，386SX能使用速度较慢或成本较低的内存，而不影响整体性能。 7. **集成的内存管理单元（MMU）**：具备虚拟内存支持，允许系统利用超过物理内存大小的地址空间，提高了系统的可扩展性和资源利用率。 8. **版权与法律声明**：文档中的版权信息和条款强调了Intel对产品销售和使用的责任限制，以及保留随时更改规格的权利。 9. **发布日期与订单号**：该Datasheet在1994年1月更新，并在1995年获得版权，订单号为240187-008。 386SX的这些特性使得它在当时成为了一个兼顾性能和成本效益的选择，尤其适合那些需要升级到32位处理能力但预算有限的系统。对于今天的硬件开发者来说，理解这些技术细节仍然有助于他们设计兼容老式硬件的系统或研究计算机历史。

Intel386

SX MICROPROCESSOR

240187–6

Figure 2.5. Intel386

SX Microprocessor Supported Data Types

Intel386

SX MICROPROCESSOR

2.7 Interrupts and Exceptions

Interrupts and exceptions alter the normal program

flow in order to handle external events, report errors

or exceptional conditions. The difference between

interrupts and exceptions is that interrupts are used

to handle asynchronous external events while ex-

ceptions handle instruction faults. Although a pro-

gram can generate a software interrupt via an INT N

instruction, the processor treats software interrupts

as exceptions.

Hardware interrupts occur as the result of an exter-

nal event and are classified into two types: maskable

or non-maskable. Interrupts are serviced after the

execution of the current instruction. After the inter-

rupt handler is finished servicing the interrupt, exe-

cution proceeds with the instruction immediately

after the interrupted instruction.

Exceptions are classified as faults, traps, or aborts,

depending on the way they are reported and wheth-

er or not restart of the instruction causing the excep-

tion is supported. Faults are exceptions that are de-

tected and serviced before the execution of the

faulting instruction. Traps are exceptions that are

reported immediately after the execution of the in-

struction which caused the problem. Aborts are ex-

ceptions which do not permit the precise location of

the instruction causing the exception to be deter-

mined.

Thus, when an interrupt service routine has been

completed, execution proceeds from the instruction

immediately following the interrupted instruction. On

the other hand, the return address from an excep-

tion fault routine will always point to the instruction

causing the exception and will include any leading

instruction prefixes. Table 2.5 summarizes the possi-

ble interrupts for the Intel386 SX Microprocessor

and shows where the return address points to.

Table 2.5. Interrupt Vector Assignments

Return Address

Interrupt

Instruction Which

Points to

Function

Number

Can Cause

Faulting

Type

Exception

Instruction

Divide Error 0 DIV, IDIV YES FAULT

Debug Exception 1 any instruction YES TRAP*

NMI Interrupt 2 INT 2 or NMI NO NMI

One Byte Interrupt 3 INT NO TRAP

Interrupt on Overflow 4 INTO NO TRAP

Array Bounds Check 5 BOUND YES FAULT

Invalid OP-Code 6 Any illegal instruction YES FAULT

Device Not Available 7 ESC, WAIT YES FAULT

Double Fault 8

Any instruction that can

ABORT

generate an exception

Coprocessor Segment Overrun 9 ESC NO ABORT

Invalid TSS 10 JMP, CALL, IRET, INT YES FAULT

Segment Not Present 11 Segment Register Instructions YES FAULT

Stack Fault 12 Stack References YES FAULT

General Protection Fault 13 Any Memory Reference YES FAULT

Page Fault 14 Any Memory Access or Code Fetch YES FAULT

Coprocessor Error 16 ESC, WAIT YES FAULT

Intel Reserved 17–32

Two Byte Interrupt 33– 255 INT n NO TRAP

*Some debug exceptions may report both traps on the previous instruction and faults on the next instruction.

Intel386

SX MICROPROCESSOR

The Intel386 SX Microprocessor has the ability to

handle up to 256 different interrupts/exceptions. In

order to service the interrupts, a table with up to 256

interrupt vectors must be defined. The interrupt vec-

tors are simply pointers to the appropriate interrupt

service routine. In Real Mode, the vectors are 4-byte

quantities, a Code Segment plus a 16-bit offset; in

Protected Mode, the interrupt vectors are 8 byte

quantities, which are put in an Interrupt Descriptor

Table. Of the 256 possible interrupts, 32 are re-

served for use by Intel and the remaining 224 are

free to be used by the system designer.

INTERRUPT PROCESSING

When an interrupt occurs, the following actions hap-

pen. First, the current program address and Flags

are saved on the stack to allow resumption of the

interrupted program. Next, an 8-bit vector is supplied

to the Intel386 SX Microprocessor which identifies

the appropriate entry in the interrupt table. The table

contains the starting address of the interrupt service

routine. Then, the user supplied interrupt service

routine is executed. Finally, when an IRET instruc-

tion is executed the old processor state is restored

and program execution resumes at the appropriate

instruction.

The 8-bit interrupt vector is supplied to the Intel386

SX Microprocessor in several different ways: excep-

tions supply the interrupt vector internally; software

INT instructions contain or imply the vector; maska-

ble hardware interrupts supply the 8-bit vector via

the interrupt acknowledge bus sequence. Non-

Maskable hardware interrupts are assigned to inter-

rupt vector 2.

Maskable Interrupt

Maskable interrupts are the most common way to

respond to asynchronous external hardware events.

A hardware interrupt occurs when the INTR is pulled

HIGH and the Interrupt Flag bit (IF) is enabled. The

processor only responds to interrupts between in-

structions (string instructions have an ‘interrupt win-

dow‘ between memory moves which allows inter-

rupts during long string moves). When an interrupt

occurs the processor reads an 8-bit vector supplied

by the hardware which identifies the source of the

interrupt (one of 224 user defined interrupts).

Interrupts through interrupt gates automatically reset

IF, disabling INTR requests. Interrupts through Trap

Gates leave the state of the IF bit unchanged. Inter-

rupts through a Task Gate change the IF bit accord-

ing to the image of the EFLAGs register in the task’s

Task State Segment (TSS). When an IRET instruc-

tion is executed, the original state of the IF bit is

restored.

Non-Maskable Interrupt

Non-maskable interrupts provide a method of servic-

ing very high priority interrupts. When the NMI input

is pulled HIGH it causes an interrupt with an internal-

ly supplied vector value of 2. Unlike a normal hard-

ware interrupt, no interrupt acknowledgment se-

quence is performed for an NMI.

While executing the NMI servicing procedure, the In-

tel386 SX Microprocessor will not service any further

NMI request or INT requests until an interrupt return

(IRET) instruction is executed or the processor is

reset. If NMI occurs while currently servicing an NMI,

its presence will be saved for servicing after execut-

ing the first IRET instruction. The IF bit is cleared at

the beginning of an NMI interrupt to inhibit further

INTR interrupts.

Software Interrupts

A third type of interrupt/exception for the Intel386

SX Microprocessor is the software interrupt. An INT

n instruction causes the processor to execute the

interrupt service routine pointed to by the n

vector

in the interrupt table.

A special case of the two byte software interrupt INT

n is the one byte INT 3, or breakpoint interrupt. By

inserting this one byte instruction in a program, the

user can set breakpoints in his program as a debug-

ging tool.

A final type of software interrupt is the single step

interrupt. It is discussed in Single Step Trap.

Intel386

SX MICROPROCESSOR

INTERRUPT AND EXCEPTION PRIORITIES

Interrupts are externally generated events. Maska-

ble Interrupts (on the INTR input) and Non-Maskable

Interrupts (on the NMI input) are recognized at in-

struction boundaries. When NMI and maskable

INTR are both recognized at the same instruction

boundary, the Intel386 SX Microprocessor invokes

the NMI service routine first. If maskable interrupts

are still enabled after the NMI service routine has

been invoked, then the Intel386 SX Microprocessor

will invoke the appropriate interrupt service routine.

As the Intel386 SX Microprocessor executes instruc-

tions, it follows a consistent cycle in checking for

exceptions, as shown in Table 2.6. This cycle is re-

peated as each instruction is executed, and occurs

in parallel with instruction decoding and execution.

INSTRUCTION RESTART

The Intel386 SX Microprocessor fully supports re-

starting all instructions after Faults. If an exception is

detected in the instruction to be executed (exception

categories 4 through 10 in Table 2.6), the Intel386

SX Microprocessor invokes the appropriate excep-

tion service routine. The Intel386 SX Microprocessor

is in a state that permits restart of the instruction, for

all cases but those given in Table 2.7. Note that all

such cases will be avoided by a properly designed

operating system.

Table 2.6. Sequence of Exception Checking

Consider the case of the Intel386 SX Microprocessor having just completed an instruction. It then performs

the following checks before reaching the point where the next instruction is completed:

1. Check for Exception 1 Traps from the instruction just completed (single-step via Trap Flag, or Data

Breakpoints set in the Debug Registers).

2. Check for external NMI and INTR.

3. Check for Exception 1 Faults in the next instruction (Instruction Execution Breakpoint set in the Debug

Registers for the next instruction).

4. Check for Segmentation Faults that prevented fetching the entire next instruction (exceptions 11 or 13).

5. Check for Page Faults that prevented fetching the entire next instruction (exception 14).

6. Check for Faults decoding the next instruction (exception 6 if illegal opcode; exception 6 if in Real Mode

or in Virtual 8086 Mode and attempting to execute an instruction for Protected Mode only; or exception

13 if instruction is longer than 15 bytes, or privilege violation in Protected Mode (i.e. not at IOPL or at

CPL

0).

7. If WAIT opcode, check if TS

1 and MP

1 (exception 7 if both are 1).

8. If ESCape opcode for numeric coprocessor, check if EM

1orTS

1 (exception 7 if either are 1).

9. If WAIT opcode or ESCape opcode for numeric coprocessor, check ERROR

input signal (exception 16

if ERROR

input is asserted).

10. Check in the following order for each memory reference required by the instruction:

a. Check for Segmentation Faults that prevent transferring the entire memory quantity (exceptions 11,

12, 13).

b. Check for Page Faults that prevent transferring the entire memory quantity (exception 14).

NOTE:

Segmentation exceptions are generated before paging exceptions.

Table 2.7. Conditions Preventing Instruction Restart

1. An instruction causes a task switch to a task whose Task State Segment is partially ‘not present‘ (An

entirely ‘not present‘ TSS is restartable). Partially present TSS’s can be avoided either by keeping the

TSS’s of such tasks present in memory, or by aligning TSS segments to reside entirely within a single 4K

page (for TSS segments of 4K bytes or less).

2. A coprocessor operand wraps around the top of a 64K-byte segment or a 4G-byte segment, and spans

three pages, and the page holding the middle portion of the operand is ‘not present‘. This condition can

be avoided by starting at a page boundary any segments containing coprocessor operands if the

segments are approximately 64K-200 bytes or larger (i.e. large enough for wraparound of the coproces-

sor operand to possibly occur).

Note that these conditions are avoided by using the operating system designs mentioned in this table.

Intel386

SX MICROPROCESSOR

Table 2.8. Register Values after Reset

Flag Word (EFLAGS) uuuu0002H Note 1

Machine Status Word (CR0) uuuuuu10H

Instruction Pointer (EIP) 0000FFF0H

Code Segment (CS) F000H Note 2

Data Segment (DS) 0000H Note 3

Stack Segment (SS) 0000H

Extra Segment (ES) 0000H Note 3

Extra Segment (FS) 0000H

Extra Segment (GS) 0000H

EAX register 0000H Note 4

EDX register component and stepping ID Note 5

All other registers undefined Note 6

NOTES:

1. EFLAG Register. The upper 14 bits of the EFLAGS register are undefined, all defined flag bits are zero.

2. The Code Segment Register (CS) will have its Base Address set to 0FFFF0000H and Limit set to 0FFFFH.

3. The Data and Extra Segment Registers (DS, ES) will have their Base Address set to 000000000H and Limit set to

0FFFFH.

4. If self-test is selected, the EAX register should contain a 0 value. If a value of 0 is not found then the self-test has

detected a flaw in the part.

5. EDX register always holds component and stepping identifier.

6. All undefined bits are Intel Reserved and should not be used.

DOUBLE FAULT

A Double Fault (exception 8) results when the proc-

essor attempts to invoke an exception service rou-

tine for the segment exceptions (10, 11, 12 or 13),

but in the process of doing so detects an exception

other than a Page Fault (exception 14).

One other cause of generating a Double Fault is the

Intel386 SX Microprocessor detecting any other ex-

ception when it is attempting to invoke the Page

Fault (exception 14) service routine (for example, if a

Page Fault is detected when the Intel386 SX Micro-

processor attempts to invoke the Page Fault service

routine). Of course, in any functional system, not

only in Intel386 SX Microprocessor-based systems,

the entire page fault service routine must remain

‘present‘ in memory.

2.8 Reset and Initialization

When the processor is initialized or Reset the regis-

ters have the values shown in Table 2.8. The In-

tel386 SX Microprocessor will then start executing

instructions near the top of physical memory, at lo-

cation 0FFFFF0H. When the first Intersegment

Jump or Call is executed, address lines A

–A

will

drop LOW for CS-relative memory cycles, and the

Intel386 SX Microprocessor will only execute in-

structions in the lower one megabyte of physical

memory. This allows the system designer to use a

shadow ROM at the top of physical memory to ini-

tialize the system and take care of Resets.

RESET forces the Intel386 SX Microprocessor to

terminate all execution and local bus activity. No in-

struction execution or bus activity will occur as long

as Reset is active. Between 350 and 450 CLK2 peri-

ods after Reset becomes inactive, the Intel386 SX

Microprocessor will start executing instructions at

the top of physical memory.

2.9 Testability

The Intel386 SX Microprocessor, like the Intel386

Microprocessor, offers testability features which in-

clude a self-test and direct access to the page trans-

lation cache.

SELF-TEST

The Intel386 SX Microprocessor has the capability

to perform a self-test. The self-test checks the func-

tion of all of the Control ROM and most of the non-

random logic of the part. Approximately one-half of

the Intel386 SX Microprocessor can be tested during

self-test.

Self-Test is initiated on the Intel386 SX Microproces-

sor when the RESET pin transitions from HIGH to

LOW, and the BUSY

pin is LOW. The self-test

takes about 2

clocks, or approximately 33 millisec-

onds with a 16 MHz Intel386 SX CPU. At the com-

pletion of self-test the processor performs reset and

begins normal operation. The part has successfully

passed self-test if the contents of the EAX are zero.

If the results of the EAX are not zero then the self-

test has detected a flaw in the part.

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