"DA14531硬件设计指南及应用注意事项"

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The DA14531 Hardware Guide provides detailed information on hardware design and packaging, including dimensions, minimal system schematics, power management, external flash configurations, PCB design considerations, and antenna design. The Application Note DA1453x Hardware Guidelines AN-B-075 offers a comprehensive reference schematic, circuit explanation, and design guidelines for Bluetooth Low Energy (BLE) applications using DA1453x SoCs. It covers important aspects such as power management, external flash integration, and antenna design to help developers create efficient and reliable BLE applications. The guide also includes information on the minimal system schematics, circuit explanation, and design considerations for an optimal hardware design. Overall, the DA14531 Hardware Guide and Application Note AN-B-075 provide valuable insights and recommendations for designing high-performance BLE applications using DA1453x SoCs.

AN-B-075

DA1453x Hardware Guidelines

Application Note

Revision 1.8

01-Dec-2022

CFR0014

9 of 48

3.1 Device Revision Numbering and Marking

The revision number of the chip can be read from the device by reading the registers mentioned in

Table 2 and Table 3. The result should be one of the options in Table 4.

Table 2: CHIP_REVISION_REG (0x50003214)

Bit

Mode

Symbol

Description

Reset

7:0

CHIP_REVISION

Chip version, corresponds with type number in ASCII

0x41 = 'A', 0x42 = 'B'.

Table 3: CHIP_TEST1_REG (0x500032F8)

Bit

Mode

Symbol

Description

Reset

7:0

CHIP_LAYOUT_

REVISION

Chip layout version, corresponds with type number in

ASCII

Table 4: Chip Revision Numbering

Commercial Number

Package

CHIP_REVISION_REG

(0x50003214)

CHIP_TEST1_REG

(0x500032F8)

DA14531-00000FX2

FCGQFN24

0x41 (A)

0x45 (E)

DA14531-00000OG2

WLCSP17

0x41 (A)

0x45 (E)

DA14531-01000FX2

FCGQFN24

0x41 (A)

0x47 (E)

DA14531-01000OG2

WLCSP17

0x41 (A)

0x47 (E)

Figure 4: DA14531 FCGQFN24 Package Marking

Figure 5: DA14531 WLCSP17 Package Marking

AN-B-075

DA1453x Hardware Guidelines

Application Note

Revision 1.8

01-Dec-2022

CFR0014

10 of 48

3.2 The DA14531 System

Only a few external components are required to have DA14531 operational. The necessary

components are:

• Inductor, 2.2 µH for internal DCDC converter. Necessary for buck and boost configuration. In

bypass configuration, the inductor can be removed

• Capacitors on VBAT_HIGH and VBAT_LOW for internal DCDC converter. Their value depends

on the DCDC configuration and the type of power source

• XTAL 32 MHz, provides the main system and BLE clock

• XTAL 32 kHz, as the low-power clock in sleep mode. When RCX (less accurate) is used, XTAL

32 kHz can be omitted

• For some applications an RF low-pass filter is required to supress spurious emissions.

• Antenna. Is either printed or ceramic

Figure 6: DA14531 System Configurations

3.2.1 The Power Section of DA14531

The DA14531 has a flexible power setup and can operate in three different power configurations:

Buck, Boost and Bypass. Depending on the available power source, Buck mode is intended for use

with higher voltage batteries, such as lithium primary cells (3 V) or 2x alkaline combinations, while

Boost mode can be used with lower voltage Silver oxide cells. In Bypass mode, the DCDC converter

is not used and because of that there is no need for an external inductor. This results in a cheaper

BOM, but also in lower power efficiency.

The power management logic is fully integrated, and the user can select the desired mode with minor

hardware modifications.

3.2.1.1 The PMU of DA14531

The DA14531 has an integrated Power Management Unit (PMU), which consists of a VDD Clamp,

Power on Reset (POR) circuitry, a DCDC converter and various LDOs.

The PMU integrates two main power rails VBAT_HIGH and VBAT_LOW, and the internal VDD power

rail.

● VBAT_HIGH voltage is in the range of 1.8 V – 3.3 V. This power rail is used for the blocks that

require a higher supply voltage. The OTP and the GPIOs are connected to this power rail. The

lowest voltage for OTP reading is 1.62 V whereas to write OTP this is 2.25 V.

VBAT_HIGH is protected by the power-on-reset circuit POR_HIGH, which will generate a Power

On Reset when the voltage drops below 1.66 V (V_IL) for more than 50 μs and will release the

reset at typically 1.75V.

● VBAT_LOW is the main system supply, with the lowest voltage equal to 1.1 V. The functional

range is between 1.1 V - 3.3 V.

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