UniversalChipletInterconnectExpress(UCIe)_UCIe协议中文

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Universal Chiplet Interconnect express (UCIe)

Specification

UCIe Specification Revision 1.0 16

Februrary 24, 2022

Property of Universal Chiplet Interconnect Express (UCIe) 2022

A UCIe Retimer may be used to extend the UCIe connectivity beyond the package using

an Off-Package Interconnect. Examples of Off-Package Interconnect include electrical

cable or optical cable or any other technology to connect packages at a Rack/Pod level

as shown in Figure 2. The UCIe specification requires the UCIe Retimer to implement

the UCIe interface to the die that it connects on its local package and ensure that the

Flits are delivered across the two dies across the packages following UCIe protocol

using the channel extension technology of its choice.

Figure 2 demonstrates a rack/pod-level disaggregation using CXL 2.0 (or later)

protocol. Figure 2a shows the rack level view where multiple compute nodes (virtual

hierarchy) from different compute chassis connect to a CXL switch which connects to

multiple CXL accelerators/Type-3 memory devices which can be placed in one or more

separate drawer. The logical view of this connectivity is shown in Figure 2b, where each

“host” (H1, H2,…) is a compute drawer. Each compute drawer connects to the switch

using an Off-Package Interconnect running CXL protocol through a UCIe Retimer, as

shown in Figure 2c. The switch also has co-package Retimers where the Retimer tiles

connect to the main switch die using UCIe and on the other side are the PCIe/CXL

physical interconnects to connect to the accelerators/memory devices, as shown in

Figure 2c.

Figure 2. UCIe enabling long-reach connectivity at Rack/Pod Level

This version of UCIe Specification does not deal with 3D packaging. It allows two

different packaging options: Standard Package (2D) and Advanced Package (2.5D).

This covers the spectrum from lowest cost to best performance interconnects.

1. Standard Package - This packaging technology is used for low cost and long

reach (10mm to 25mm) interconnects using traces on organic package/substrate,

while still providing significantly better BER characteristics compared to off-package

SERDES. Figure 3 shows an example application using the Standard Package

option. Ta bl e 4 shows a summary of the characteristics of the Standard Package

option with UCIe.

Universal Chiplet Interconnect express (UCIe)

Specification

UCIe Specification Revision 1.0 19

Februrary 24, 2022

Property of Universal Chiplet Interconnect Express (UCIe) 2022

Figure 7. UCIe Layers and functionalities

1.1.1 Protocol Layer

While the Protocol Layer may be application specific, UCIe specification provides

examples of transferring CXL or PCIe protocols over UCIe Links. The following protocols

are supported in UCIe for enabling different applications:

• PCIe 6.0 Flit Mode from PCI Express Base Specification.

• CXL 2.0 and later protocols from Compute Express Link Specification.

• Streaming Protocol: This offers generic modes for a user defined protocol to be

transmitted using UCIe.

For each protocol, different optimizations and associated Flit transfers are available for

transfer over UCIe. Chapter 2.0 and Chapter 3.0 cover the relevant details of different

modes and Flit formats.

1.1.2 Die-to-Die (D2D) Adapter

The D2D Adapter coordinates with the Protocol Layer and the Physical Layer to ensure

successful data transfer across the UCIe Link. It minimizes logic on the main data path

as much as possible giving a low latency, optimized data path for protocol Flits. When

transporting CXL protocol, the ARB/MUX functionality required for multiple

simultaneous protocols is performed by the D2D Adapter. For options where the Raw

BER is less than 1e-27, a CRC and Retry scheme are provided in the UCIe specification,

which is implemented in the D2D Adapter. Refer to section 3.7 for Retry rules.

D2D Adapter is responsible for coordinating higher level Link state machine and bring

up, protocol options related parameter exchanges with remote Link partner, and when

supported, power management coordination with remote Link partner. Chapter 3.0

covers the relevant details for the D2D Adapter.

PHY Logic

Raw D2D interface

ARB/MUX (when applicable)

CRC/Retry (when applicable)

Link State Management

Parameter Negotiation

Die‐to‐Die Adapter

Link Training

Lane Repair (when applicable)

Lane Reversal (when applicable)

Scrambling/De‐scrambling (opt‐in)

Sideband Training and transfers

Analog Front End

Clock forwarding

Electrical/AFE [k slices]

Sideband/

Global

Flit aware

D2D interface

Protocol Layer

Physical Layer

(FDI)

(RDI)

Universal Chiplet Interconnect express (UCIe)

Specification

UCIe Specification Revision 1.0 20

Februrary 24, 2022

Property of Universal Chiplet Interconnect Express (UCIe) 2022

1.1.3 Physical Layer

The Physical Layer has three sub-components as shown in Figure 8:

Figure 8. Physical Layer components

UCIe’s main data path on the physical bumps is organized as a group of Lanes called a

Module. A Module forms the atomic granularity for the structural design implementation

of UCIe’s AFE. The number of Lanes per Module for Standard and Advanced package is

specified in Chapter 4.0.

A given instance of Protocol Layer or D2D adapter can send

data over multiple modules where bandwidth scaling is required.

The physical Link of UCIe comprises of two connections:

1. Sideband:

This connection is used for parameter exchanges, register accesses for debug/

compliance and coordination with remote partner for Link training and

management. It consists of a forwarded clock pin and a data pin in each direction.

The clock is fixed at 800MHz regardless of the main data path speed. The sideband

logic for UCIe’s Physical Layer must be on auxiliary power and an "always on"

domain. Each module has its own set of sideband pins.

For the Advanced Package option, a redundant pair of clock and data pins in each

direction is provided for repair.

2. Main-band:

This connection constitutes the main data path of UCIe. It consists of a forwarded

clock, a data valid pin, and N Lanes of data per module.

For the Advanced Package option, N=64 (also referred to as x64) and overall four

extra pins for Lane repair are provided in the bump map.

For the Standard Package option, N=16 (also referred to as x16) and no extra pins

for repair are provided.

The Logical Physical Layer co-ordinates the different functions and their relative

sequencing for proper Link bring up and management (for example, sideband

transfers, main-band training and repair etc.). Chapter 4.0 and Chapter 5.0 cover the

details on Physical Layer operation.

1.1.4 Interfaces

UCIe defines the interfaces between the Physical Layer and the D2D Adapter (Raw D2D

Interface), and the D2D Adapter and the Protocol Layer (Flit-aware D2D Interface) in

Chapter 8.0.

PHY Logic

Raw D2D interface

FIFO & SERDES

Clocking & Tx/Rx

Electrical/AFE [k slices]

Sideband

(x M)

K x N

Sideband/

Global 1 slice

ValidFW‐CLK

Link Training

Lane Repair (when applicable)

Lane Reversal (when applicable)

Scrambling/De‐scrambling (opt‐in)

Sideband Training and transfers

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【UCIe】UCIe 协议层介绍

UCIe-Rev1p0-Consortium-Feb24th-2022-Final

Chiplet技术研究与展望.docx

UCIe（Universal Chiplet Interconnect Express）的电气物理层有什么作用？对于验证人员来说它能提供什么帮助？

Universal Chiplet Interconnect Express中为什么要使用均衡技术？有什么作用？具体实现是什么？

Universal Chiplet Interconnect Express中解释一下什么是点到点的 DC 耦合？

问的就是Universal Chiplet Interconnect Express的电气物理层有什么作用？对于验证人员来说它能提供什么帮助？

Universal Chiplet Interconnect Express发送端可以采用预加重和去加重的均衡技术，分别解释一下？并说明其在电路上的区别？

Universal Chiplet Interconnect Express 接收端可以采用 CTLE、Inductive Peaking 或一阶 DFE 做均衡。分别解释一下CTLE、Inductive Peaking 或一阶 DFE？

Universal Chiplet Interconnect Express中解释一下什么是模块内匹配长度的互联设计？什么是先进封装时为 Unterminated，标准封装支持 Rx Terminated 及 Unterminated？

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