Tutorial
percent.) We note that because the input frequency,
Win,
is momentarily greater than the output frequency,
WoUh
x(t)
accumulates phase faster than does
y(t)
and the PO generates increasingly wider pulses. Each
of
these pulses creates an
increasingly higher de voltage at the output of the LPF, thereby increasing the
veo
frequency. As the difference between
Win and
Wout
diminishes, the width of the phase comparison pulses decreases, eventually returning to slightly greater than its
value before
t = to.
x(t)
y{t)
PO
Output
LPF
Output
Fig. 13 Response of a PLL to a small frequency step.
The above analysis provides insight into the "tracking" capabilities of a PLL. If the input frequency changes slowly,
its variation can be viewed as a succession of small narrow steps, during each of which the PLL behaves as in Figure 13.
It is important to note that in the above example the loop locks only after two conditions are satisfied: 1)
Wout
has
become equal to
Win,
and 2) the difference between (j>in and (j>out has settled to its proper value [1]. If the two frequencies
become equal at a point in time but
~(j>
does not establish the required control voltage for the
YeO,
the loop must continue
the transient, temporarily making the frequencies unequal again. In other words, both "frequency acquisition" and "phase
acquisition" must be completed. This is, of course, to be expected because for lock to occur again, all the initial conditions
of the system, including the
veo
output phase, must be updated.
If the input to a PLL has a constant excess phase, i.e., is strictly periodic, but the input/output phase error,
~l/J,
varies
with time, we say the loop is "unlocked," an undesirable state because the output does not track the input or the relationship
between the input and output is too complex to be useful. For example, if
Win is sufficiently far from the
YeO's
free-running
frequency, the loop may never lock. While the behavior of a PLL in the unlocked state is not important per se, whether and
how it enters the locked state are both critical issues. Acquisition of lock is explained in Section 4.4.
Before studying PLLs in more detail, we make three important observations. First, because a PLL is a system with
"memory," its output requires a finite time to respond to a change at its input, mandating a good understanding
of
the loop
dynamics. Second, in a PLL, unlike many other feedback systems, the variable
of
interest changes dimension around the
loop: it is converted from phase to voltage (or current) by the phase detector, processed by the LPF as such, and converted
back to phase by the
Yeo.
Third, in the lock condition, the input and output frequencies are exactly equal, regardless
of
the
magnitude
of
the loop gain (although the phase error may not be zero). This is an extremely important property because
many applications are intolerant of even small (systematic) differences between the input and output frequencies. Note that
if the phase detector is replaced with only a frequency detector, this property vanishes.
"Whilea
PLL
operates on phase, in many cases the parameter of interest is frequency. For example, we often need
to know the response of the loop if 1) the input frequency is varied slowly, 2) the input frequency is varied rapidly, or 3)
the input and output frequencies are not equal when the PLL is turned on. Therefore, the phase detector characteristic for
unequal input frequencies plays an important role in the behavior of a phase-locked loop.
4.2 Loop Dynamics in LockedState
Transient response of phase-locked loops is generally a nonlinear process that cannot be formulated easily. Never-
theless, as with other feedback systems, a linear approximation can be used to gain intuition and understand trade-offs in
PLL design.
Figure 14 shows a linear model of the PLL in lock along with the transfer function
of
each block. The model is to
provide the overall transfer function for the phase,
<I>
out
(s)
/
<I>
in
(s);
hence, the PD is represented by a subtractor. The LPF is
assumed to have a voltage transfer function
GLPF(S). The open-loop transfer function of the PLL is therefore equal to
Kvco
Ho(s)
=
KpOGLPF(S)--
(17)
S
7
剩余38页未读，继续阅读
maojoujou
- 粉丝: 4
- 资源: 5
我的内容管理
展开
最新资源
- BGP协议首选值(PrefVal)属性与模拟组网实验
- C#实现VS***单元测试coverage文件转xml工具
- NX二次开发：UF_DRF_ask_weld_symbol函数详解与应用
- 从机FIFO的Verilog代码实现分析
- C语言制作键盘反应力训练游戏源代码
- 简约风格毕业论文答辩演示模板
- Qt6 QML教程：动态创建与销毁对象的示例源码解析
- NX二次开发函数介绍：UF_DRF_count_text_substring
- 获取inspect.exe：Windows桌面元素查看与自动化工具
- C语言开发的大丰收游戏源代码及论文完整展示
- 掌握NX二次开发：UF_DRF_create_3pt_cline_fbolt函数应用指南
- MobaXterm：超越Xshell的远程连接利器
- 创新手绘粉笔效果在毕业答辩中的应用
- 学生管理系统源码压缩包下载
- 深入解析NX二次开发函数UF-DRF-create-3pt-cline-fcir
- LabVIEW用户登录管理程序：注册、密码、登录与安全
资源上传下载、课程学习等过程中有任何疑问或建议，欢迎提出宝贵意见哦~我们会及时处理！
点击此处反馈
