MCS-51微控制器家族用户手册：高级特性与应用指南

需积分: 9 157 浏览量更新于2024-07-07 收藏 14.92MB PDF 举报

MCS-51微控制器家族用户手册是一份详细介绍Intel 8051核心微处理器系列的文档，该系列以其在控制应用中的优化性能而闻名。8051是一款8位CPU，它具有强大的布尔逻辑处理能力，特别适合于需要高度控制和逻辑操作的场景。该芯片集成了64KB的程序存储空间和64KB的数据存储空间，提供充足的内存资源。核心特点包括： 1. 64KB程序存储空间：为复杂算法和程序设计提供了足够的空间，满足了大多数控制系统的存储需求。 2. 4KB的内部程序存储器：对于小型系统来说，这是非常宝贵的，减少了外部存储的需求。 3. 128字节的内部数据RAM：用于临时数据存储和高速处理，提高了处理速度和效率。 4. 32条双向和独立寻址的I/O线：这些I/O接口支持丰富的外设连接，方便与外部设备通信。 5. 两个16位定时器/计数器：支持精确的时间测量和周期性任务的执行，广泛应用于定时、计数和脉冲发生器等应用。 6. 全双工串行通信接口（UART）：允许数据的双向传输，支持远程通信和数据交换。 7. 6源/5向量中断结构：具有两个优先级级别，可以有效管理多个并发事件，提高系统的响应速度和实时性。 8. 内置时钟振荡器：确保了稳定的时钟信号，是实现精准时间同步的基础。 MCS-51微控制器家族是Intel针对特定市场开发的一系列产品，它们共享8051的核心架构，因此所有MCS-51设备都具备这些核心特性。这份用户手册提供了详细的操作指南和技术规范，帮助用户了解如何充分利用这些功能来构建高效、可靠的控制系统。用户在使用前应确保查阅最新规格，因为Intel有权随时更新规格，以适应技术的进步。此外，手册还强调了其他品牌和商标的归属权，以及Intel Corporation提供的文献获取渠道。MCS-51微控制器因其高性能和广泛的适用性，在工业控制、嵌入式系统设计等领域占据着重要的地位。

MCS@-51 ARCHITECTURAL OVERVIEW

The bits RSOand RSl are wed to select one of the four

tions refer to these RAM locations as RO through R7.

The selection of which of the four banks is being re-

ferred to is made on the basis of the bits RSOand RS1

at execution time.

The Parity bit reflects the number of 1s in the Accumu-

lator P = 1 if the Accumulator contains an odd num-

ber of 1s, and P = O if the Accumulator contains an

even number of 1s. Thus

thenumber of 1s in the Accu-

mulator plus P is always even.

Two bits in the PSW are uncommitted and maybe used

as general purpose status flags.

Addressing Modes

The

addressing modes in the MCS-51 instruction set

are as follows

DIRECT ADDRESSING

In direct addressing the operand is specitied by an 8-bit

addreas field in the instruction. Only internal Data

RAM and SFRS can be directly addressed.

INDIRECT ADDRESSING

In indirect addressing the instruction specifies a register

which contains the address of the operand. Both inter-

nal and external RAM can be indirectly addressed.

The address register for 8-bit addresses can be RO or

RI of the selected register bank, or the Stack Pointer.

The addreas register for id-bit addresses can only be the

id-bit “data pointer” register, DPTR.

The

can be accemed by certain instructions which carry a

3-bit register specification within the opcode of the in-

struction. Instructions that access the registers this way

are code efficient, since this mode elirninatez an addreas

byte. When the instruction is executedj one of the eight

registers in the selected bank is amessed. One of four

banks is selected at execution time by the two bank

select bits in the PSW.

Some instructions are specific to a certain register. For

example, some instructions always operate on the Ac-

cumulator, or Data Pointer, etc., so no address byte is

needed to point to it. The opcode itself does

that.In-

structions that refer to the Accurrdator as A assemble

as accumulator-specific opcmdes.

IMMEDIATE CONSTANTS

The value of

a constant can follow the opcode in Pro-

gram Memory. For example,

MOV A, # 100

loads the Accumulator with the decimal number 100.

The same number could be specified in hex digitz as

64H.

INDEXED ADDRESSING

only

Program Memory can be amessed with indexed

addressing, and it can only be read. This addressing

mode is intended for reading look-up tables in Program

Memory. A Id-bit base register (either DPTR or the

Program Counter) points to the base of the table, and

the Accumulator is setup with the table entry number.

The address of the table entry in Program Memory is

formed by adding the Accumulator data to the base

pointer.

Another type of indexed addreaaing is used in the “case

jump” instruction. In this case the destination address

of a jump instruction is computed as the sum of the

base pointer and the Accumulator &ta.

Arithmetic Instructions

The

menu of arithmetic instructions is listed in Table 2.

The table indicates the addressing modes that can be

used with each instruction to access the <byte> oper-

and. For example, the ADD A, <byte> instruction can

be written as

ADD A,7FH

(directaddressing)

ADD A,@RO (indirect addressing)

ADD A,R7 (register addressing)

ADD A,# 127 (iediate constant)

The execution times listed in Table 2 assume a 12 MHz

clock frequency. All of the arithmetic instructions exe-

cute in 1 ps except the INC DPTR instruction, which

takes 2 W, snd the Multiply and Divide instructions,

which take 4 ps.

Note that any byte in the internal Data Memory space

can be incremented or decremented without going

through the Accumulator.

One of the INC instructions operates on the Id-bit

Data Pointer. The Data Pointer is used to generate

16-bit addresses for external memory, w being able to

increment it in one 16-bit operation is a usefirl feature.

The MUL AB instruction multiplies the Accumulator

by the data in the B register and puts the Id-bit product

into the concatenated B and Accumulator registers.

1-1o

inl#

MCS@-51 ARCHITECTURAL OVERVIEW

Table 2 A Ust of the MCS@I-51 Arithmetic Instructions

Mnemonic Operation

Addressing Modes

Execution

Dk I Ind Rq lmm

Time (@

ADD A, <byte> A = A + <byte>

x x

I ADDOA, <byte> I A= A+< byte>+C I X I X I X I X ] 1 I

SUBB A, <byte> A= A–<byte>-C

x x

x 1

INC A

I A=A+l I Accumulator onlv I 1

I INC . <byte>

<byte> =<byte>+l I X I X I X I

11-1

I lhJC DPTR I DPTR = DpTR + 1 I

Data Pointer only

121

I DEC A

I A= A-l

Accumulator only

Ill

DEC <byte>

<byte> = <byte> – 1

x x

MUL

AB B.A=Bx A ACC and B only 4

DIV AB

A = Int [A/B]

B = MOd [A/Bl

ACC and

B only

IDAA I Decimal Adjust

Accumulatoronly

Ill

The DIV AB instruction divides the Accumulator by

the data in the B register and leevea the 8-bit quotient

in the Accumulator, and the 8-bit remainder in the B

Oddly enough, DIV AB finds lees use in arithmetic

“divide” routines than in radix eonversions and pro-

~ble shift operstioILs.k example of the use of

DIV AB in a radix conversion will be given later. In

s~ operations, dividing a number by 2n shifts its n

bits to the right. Using DIV AS to perform the division

eompletcs the shift in 4 p.s and leaves the B register

holding the bits that were shifted out.

The DA A instruction is for BCD arithmetic opera-

tions. In BCD arithmetic, ADD and ADDC instruc-

tions should always be followed by a DA A operation,

to ensure that the

red is also in BCD. Note that DA

A will not convert a binary number to BCD. The DA

A operation produces a meaningfid

result only as the

second step in the addition of two BCD bytes.

Table 3. A Uet of the MCS@J-51Logical Instructions

Mnemonic

Operation

Addressing Modes

Execution

Dir

Ind I Reg I

Imm

Time (ps)

ANL A,< byte> A = A .AND. <byte> x x x x

ANL <byte>,A

<byte> = <byte> .AND. A

x 1

ANL <bvte>, #data

.AND. #data

x 2

ORL A,< byte>

A = A.OR. <byte>

X1X1X1X

ORL <bvte>,A

<byte> = <byte> .OR.A

x 1

ORL <byte>, #data

<byte> = <byte> .OR. #data

XRL A,< byte> A = A .XOR. <byte> X1X1X

XRL <byte>,A

<byte> = <byte> .XOR. A

XRL <byte>, #data

<byte> = <byte> .XOR. #data I X

CRL A

A=OOH

Accumulator only 1

CPL A

A =

.NOT. A

Accumulator

only

IRL A I Rotate ACC Left 1 bit I

Accumulator onlv

Ill

RLC A

Rotate Left through Csrry

Accumulator only

RR A

Rotate ACC Right

1 bit

Accumulator only 1

RRC A

Rotate Right through Carry

Accumulator only 1

SWAP A

Swap Nibbles in A

Accumulator

onlv 1

1-11

irrtel.

MCS@-51 ARCHITECTURAL OVERVIEW

Logical Instructions

Table 3 shows the list ofMCS-51 logical instructions.

The instructions that perform Boolean operations

(AND, OIL Exclusive OIL NOT) on bytes perform the

operation on a bit-by-bit bssis. That is, if the Aecumu-

Iator contains 001101OIB and <byte> contains

O1OIOOIIB,then

ANL

A, <byte>

will leave the Accumulator holding OOO1OOOIB.

The addrcasing modes that can be used to access the

<byte> operand are

listedinTable 3. Thus, the ANL

A, <byte> instruction may take any of the forms

ANL A,7FH (direct addressing)

ANL A,@Rl

(indirect addressing)

ANL

A,R6 (register addressing)

ANL

A, # 53H (immediate constant)

AU of the logical instructions that are Accumulator-

specflc execute in lps (using a 12 MHz clock). The

othem take 2 ps.

Note that Boolean operations can be performed on any

byte in the lower 128 internal Data Memory space or

the SFR space using direct addressing, without having

to use the Accumulator. The XRL <byte >, #data in-

struction, for example offets a quick and easy way to

invert port bits, as in

XRL Pl,#oFFH

If the operation is in response to an interrupt, not using

the Accumulator saves the time and effort to stack it in

the service routine.

The Rotate instructions (3U & RLC A, etc.) shift the

Aeeurtmlator 1 bit to the MI or right. For a left rota-

tion, the MSB rolls into the LSB position. For a right

rotation, the LSB rolls into the MSB position.

The SWAP A instruction interchanges the high and

low nibbles within the Accumulator. This is a useful

operation in BCD manipulations. For exampie+ if the

Accumulator contains a binary number which is known

to be leas thsn IQ it can be qnickly converted to BCD

by the following code:

MOV B,# 10

DIV AB

SWAP A

ADD A,B

Dividing the number by 10 leaves the tens digit in the

low nibble of the Accumulator, and the ones digit in the

B register. The SWAP and ADD instructions move the

tens digit to the high nibble of the Accumulator, and

the onea digit to the low nibble.

Data Transfers

INTERNAL RAM

Table 4 shows the menu of instructions that are avail-

able for moving data around within the internal memo-

ry spaces, and the addressing modes that can be used

with each one. Wkh a 12 MHz clock, all of these in-

structions execute in either 1 or 2 ps.

The MOV < dest >, < src > instruction allows dats to

be transferred between any two internal RAM or SFR

lwations without going through the Accumulator. Re-

member the Upper 128 byes of data RAM can be ac-

wased only by indirect addressing, and SFR space only

by direct addressing.

Note that in all MCS-51 devices, the stack resides in

on-chip RAM, and grows upwards. The PUSH instruc-

tion first increments the Stack Pointer (SP), then copies

the byte into the stack. PUSH and POP use only dkcct

addressing to identify the byte being

saved or restored,

Table 4. A List of the MCS@-51 Data Tranafer Instructions that Access Internal Data Memory Space

Mnemonic Operation

Addressing Modes

Execution

Dir

Ind Reg

Imm

Time (ps)

MOV A, <src>

A = <src>

x x x x

MOV <cleat> ,A

<dest> = A

x x x

MOV <dest>, <src>

x x x x

MOV DPTR,#data16

DPTR = 16-bit immediate constant.

PUSH <WC>

INCSP: MOV “@’SP’, <src>

POP

<dest>

MOV <dest>, “@SP”: DECSP x

XCH A, <byte>

ACC and <byte> exchange data

x x x

XCHD A,@Ri

ACC and @Riexchange low nibbles

1-12

i~o

MCS@-51 ARCHITECTURAL OVERVIEW

but the stack itself is accessed by indirect addressing

using the SP register. This means the stack can go into

the Upper 128, if they are implemented, but not into

SFR space.

In devices that do not implement the Upper 128,if the

SP points to the Upper 128,PUSHed bytes are lost, and

POPped bytes are indeterminate.

The Data Transfer instructions include a id-bit MOV

that can be used to initialise the Data Pointer (DPTR)

for look-up tables in Program Memory, or for Id-bit

external Data Memory accesw.

The XCH A, <byte> instruction causes the Amu-

lator snd addressed byte to exchsnge data. The

XCHD

A,@Ri instruction is similar, but only the low nibbles

are involved in the exchange.

To see how XCH and XCHD can be used to fatitate

data manipulations, consider first the problem of shit%-

ing an 8digit BCD number two digits to the right. Fig-

ure 11 shows how this can be done using direct MOVS,

and for comparison how it can be done using XCH

instructions. To aid in understanding how the code

works, the contents of the registers that are holding the

BCD number and the content of the Accumulator are

shown alongside each instruction to indicate their

status after the instruction has been executed.

n3JMm

MOV A,2EH

MOV 2EH2DH % ;; : % ~

MOV 2CH:2BH 00 12

(a) Using direct MOVS 14 bytes, 9 ps

(b) Using XCHS 9 bytes, 5 ps

. .

Figure 11. Shifting a BCD Number

Two Dlgite to the Right

Atler the routine has been executed, the Accumulator

contains the two digits that were shitled out on the

right. Doing the routine with direct MOVSuses 14code

bytes and 9 ps of execution time (assuming a 12 MHs

clock). The same operation with XCHS uses less code

and executes almost twice as fast.

To right-shift by an odd number of digits, a one-digit

shift must be executed. Figure 12 shows a sample of

code that will right-shii a BCD number one digi~ us-

ing the XCHD instruction. Again, the contents of the

registers holding the number and of the Accumulator

areshownalongsideeachinstruction.

MOV Rl, #2EH

MOV RO,#2DH

loop for R1 = 2EH

.00P MOV A,@Rl 00 12 34 56 78 76

XCHD A,@RO

00 12 34 56 78 76

SWAP A

00 12 34 58 78 67

MOV @Rl,A

00 12 34 58 67 67

DEC RI

00 12 34 58 67 67

DEC RO

00 12 34 56 67 67

CJNE Rl,#2AH,LOOP

Imp for RI = 2DH

00 12 36 45 67 45

loop for R1 = 2CH:

00 18 23 45 67 23

ioop for RI = 2BH:

01 22 45 67 01

CLR A

01 23 45 67 00

XCH A,2AH

00 01 23 45 67 06

Figure 12. Shifting a SCD Number

One Digit to the Right

First, pointers RI and ROare setup to point to the two

bytea containing the last four BCD digits. Then a loop

is executed which leaves the last byte, location 2EIL

holding the last two digits of the shifted number. The

pointers are decrernented, and the loop is repeated for

location 2DH. The CJNE instruction (Compare and

Jump if Not Equal) is a loop control that will be de-

scribed later.

The loop is executed from LOOP to CJNE for R1 =

2EH, 2DH, 2CH and 2BH. At that point the digit that

was originally shii out on the right has propagated

to location 2AH. Siice that location should be left with

0s, the lost digit is moved to the Accumulator.

1-13

M~@.51 ARCHITECTURAL OVERVIEW

EXTERNAL RAM

Table 5 shows a list of the Data Transfer inatmctions

that acceas external Data Memory. Only indirect ad-

&easing can be used. The choice is whether to use a

one-byte address, @M where Ri can be either RO or

RI of the selected register bank, or a two-byte address,

@DPTR. The disadvantage to using 16-bit addresses if

only a few K

bytesof externalRAMare involvedis

that

16-bit addresses use alf 8 bits of Port 2 as addreas

bus. On the other hand, S-bit addresses allow one to

address a few K bytes of RAM, as shown in Figure 5,

without having to sacrifice all of Port 2.

Alf of these instructions execute in 2 pa, with a

12 MHz clock.

Tabfe 5. A

List of the MCS@-51 Data

Trsnafer Instructions that Accees

Extarnsl Data Memory Spaoe

Address

Mnemonic

Operation

Execution

Width

Time (*)

8 b~

MOVX A,@’Ri

Read external ~

RAM @Ri

8 bb MOVX @Ri,A

Write external

RAM @Ri

Read external

‘6 bns ‘ovx “@DpTR

RAM @DPTR

16 bfia

Writa exlemal

‘ovx ‘DmR’A

RAM @DPTR

Note that in all external Data RAM acaases, the Ac-

cumulator is always either the destination or source of

the data.

The read and write strobes to external RAM are acti-

vated only during the execution of a MOVX instruc-

tion. Normally these signals are inactive and in fact if

they’re not going to be used at u their pins are avail-

able as extra 1/0 lines. More about that later.

LOOKUP TABLES

Table 6 shows the two instructions that are available

for reading lookup tables in Program Memory. Since

these instructions access only Program Memory, the

lookup tablea can only be read, not updated. The nme-

monic is MOVC for “move constant”.

If the table access is to external Program Memory, then

the read strobe is PSEN.

Table 6. Tha MCS3’-51 Lookup

Table Read Inetmctions

at (A + PC) -

The first MOVC instruction in Table 6 can accommo-

date a table of up to 256 entries, numbered Othrough

255. The number of the desired entry is loaded into the

Accumulator, and the Data Pointer is setup to point to

beginning of the table. Then

MOVC A,@A+DPTR

copies the desired table entry into the Accumulator.

The other MOVC instruction works the same way, ex-

cept the Program Counter (PC) is used as the table

base, and the table is accewed through a subroutine.

First the number of the desired entry is loaded into the

Accumulator, and the subroutine is cslled:

MOV &ENTRY_NUMBER

CALL TABLE

The subroutine “TABLE” would look like this:

TABLE: MOVC A,@A + PC

The table itself immediately follows the RET (return)

instruction in Program Memory. This type of table can

have up to 255 entries, numbered 1through 255. Num-

ber Ocan not be used, because at the time the MOVC

instruction is executed, the PC contains the address of

the RET instruction. An entry numbered O would be

the RET opcode itseff.

Boolean Instructions

MCS-51 devices contain a complete Boolean (single-bit)

processor. The internal RAM contains 128addressable

bits, and the SFR space can support up to 128 other

addressable blta. Afl of the port lines are bWaddress-

abl% and each one csn be treated as a separate single-

blt port. The instructions that access these bits are not

just conditional branches, but a complete menu of

move, aeL clear, complement, OR and AND instmc-

tions. These kinds of bit operations are not essily ob-

tained in other architectures with any amount of byte-

Oriented Sottware.

1-14

剩余333页未读，继续阅读

mypc56

粉丝: 5
资源: 51

MCS-51微控制器家族用户手册：高级特性与应用指南

MCS-51手册

80C51官方手册

MCS-51单片机实验系统用户手册

MCS-51系列单片机技术手册

mcs-51单片机智能台灯

MCS-51单片机开发攻略

MCS-51单片机温度控制系统

MCS-51单片机实验指导书

MCS-51单片机汇编资料大全

MCS-51单片机系统原理及应用

最新资源