Vivado Design Suite UG903用户指南：约束使用详解

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UG903《Vivado设计套件用户指南》是一份详细的文档，针对Xilinx的Vivado Design Suite提供深入的使用约束的指导。该文档于2022年6月1日更新至v2022.1版本，旨在创建一个包容性更强的产品环境，消除非包容性语言，并促进平等和无偏见的沟通。尽管在更新过程中可能仍存在旧产品中的非包容性用语，Xilinx正在努力与行业标准保持一致。该指南共分为四章： 1. **介绍**：本章首先概述了从传统UCF约束向XDC约束的迁移，帮助用户理解为何需要转换以及如何进行这种转变。此外，它还介绍了通过设计流程导航文档的方法，以便用户能根据设计过程的不同阶段找到所需信息。 2. **约束方法论**：第二章详述了约束方法论，包括如何组织和管理设计约束。它教导用户如何有序地编写和输入约束，确保它们对逻辑综合和实施阶段的有效性。这部分重点讲解了创建synthesis（逻辑综合）约束和implementation（实现）约束的步骤，以及如何通过约束范围的设置提高效率。 3. **定义时钟**：时钟是数字系统的关键组成部分，第三章专门探讨如何在Vivado中定义时钟，包括主时钟和其他辅助时钟的配置。这部分内容对于正确的时间同步和性能优化至关重要。 4. **关于XDC约束**：作为核心内容，XDC（Extended Design Constraints）是一种高级的硬件描述语言，用于在Vivado中精确地指定设计的特性。XDC不仅涉及基本的信号连接和时序要求，还包括了高级功能如功耗管理、面积优化等。 UG903《Vivado设计套件用户指南：使用约束》是一份实用的参考手册，涵盖了从约束理论到实践操作的方方面面，对于使用Vivado进行芯片设计的工程师来说，理解和掌握这些约束技巧是提升工作效率和设计质量的关键。随着Xilinx致力于创建一个更包容的产品环境，这份文档也反映了行业发展趋势，强调了在设计过程中考虑多样性和平等的重要性。

For IP XDC les that belong to the same PROCESSING_ORDER group, the order is determined

by import or creaon sequence of the IP cores. This order cannot be changed aer the project

has been created.

Finally, the relave order between user groups and IP XDC PROCESSING_ORDER groups are as

follows:

1. User Constraints marked as EARLY

2. IP Constraints marked as EARLY (default)

3. User Constraints marked as NORMAL

4. IP Constraints marked as LATE (contain clock dependencies)

5. User Constraints marked as LATE

Note: IP XDC les that have their PROCESSING_ORDER set to LATE (in order to be processed aer the

user constraints) are named <IP_NAME>_clocks.xdc.

The following gure shows an example of how to set the PROCESSING_ORDER property:

Figure 4: Setting the XDC File PROCESSING_ORDER Example

The equivalent Tcl command is:

set_property PROCESSING_ORDER EARLY [get_files wave_gen_pins.xdc]

RECOMMENDED:

Use the

report_compile_order -constraints

  command in the Tcl Console

to report the XDC les read sequence determined by the tool based the properes menoned above,

including IS_ENABLED, USED_IN_SYNTHESIS, and USED_IN_IMPLEMENTATION.

Note: When an IP is synthesized Out of Context, the IP provides, when needed, an _ooc.xdc le which

contains the default clock denion. The _ooc.xdc has the USED_IN property set to "synthesis

out_of_context implementaon" (order does not maer). During the Out Of Context synthesis, the _ooc

le is always processed before all other constraints.

Changing Read Order

To change the read order of an XDC le or unmanaged Tcl script in a constraints set:

1. In the Sources window, select the XDC le or Tcl script you want to move.

2. Drag and drop the le to the desired posion in the constraints set.

Chapter 2: Constraints Methodology

UG903 (v2022.1) June 1, 2022 www.xilinx.com

Using Constraints 16

Send Feedback

When you open your design, the log le shows that the IP XDC le was loaded last:

Parsing XDC File [C:/project_wave_gen_hdl.srcs/sources_1/ip/clk_core/

clk_core.xdc] for cell 'clk_gen_i0/clk_core_i0/inst'

Finished Parsing XDC File [C:/project_wave_gen_hdl.srcs/sources_1/ip/

clk_core/clk_core.xdc] for cell 'clk_gen_i0/clk_core_i0/inst'

Parsing XDC File [C:/project_wave_gen_hdl.srcs/sources_1/ip/char_fifo/

char_fifo/char_fifo.xdc] for cell 'char_fifo_i0/U0'

Finished Parsing XDC File [C:/project_wave_gen_hdl.srcs/sources_1/ip/

char_fifo/char_fifo/char_fifo.xdc] for cell 'char_fifo_i0/U0'

Parsing XDC File [C:/project_wave_gen_hdl.srcs/constrs_1/imports/verilog/

wave_gen_timing.xdc] Finished Parsing XDC File [C:/

project_wave_gen_hdl.srcs/constrs_1/imports/verilog/wave_gen_timing.xdc]

Parsing XDC File [C:/project_wave_gen_hdl.srcs/sources_1/ip/char_fifo/

char_fifo/char_fifo_clocks.xdc

] for cell 'char_fifo_i0/U0'

Finished Parsing XDC File [C:/project_wave_gen_hdl.srcs/sources_1/ip/

char_fifo/char_fifo/char_fifo_clocks.xdc

] for cell 'char_fifo_i0/U0' Completed Processing XDC Constraints

Unlike with the User XDC les, you cannot directly change the read order of the IP XDC les that

belong to the same PROCESSING_ORDER group. If you must modify the order, do the following:

1. Disable the corresponding IP XDC les (IS_ENABLED set to false).

2. Copy their content.

3. Paste the content into one of the XDC les included in your constraints set.

4. Update the copied IP XDC commands with the full hierarchical netlist object path names

wherever needed. Doing so is required because the IP XDC constraints are wrien in such a

manner that they can be scoped to the IP instance.

5. Review the get_ports queries that are processed in a special way for scoped constraints. For

more informaon on XDC scoping, see Constraints Scoping.

Entering Constraints

The Vivado IDE provides several ways to enter constraints. Unless you directly edit the XDC le

in a text editor, you must open a design database (elaborated, synthesized or implemented) in

order to access the constraints windows in the Vivado IDE.

Saving Constraints in Memory

You must have a design in memory to validate your constraints during eding. When you edit a

constraint using the Vivado IDE user interface, the equivalent XDC command is issued in the Tcl

Console in order to apply it in memory. An edited ming constraint must be applied in memory

before it can be saved to the XDC le.

Chapter 2: Constraints Methodology

UG903 (v2022.1) June 1, 2022 www.xilinx.com

Using Constraints 18

Send Feedback

Before you can run synthesis or implementaon, you must save the constraints in memory back

to an XDC le that belongs to the project. The Vivado IDE prompts you to save your constraints

whenever necessary.

Do one of the following to save your constraints manually:

• Click Save Constraints.

• Select File → Constraints → Save.

Note: When you save the in-memory constraints, a dialog box opens to remind you that this could cause

the synthesis and implementaon to go out of date. Select the Remember Preference check box on this

dialog box to disable future instances of this warning.

When you run these commands, Vivado does the following:

• Saves all new constraints to the XDC le marked target in the constraints set associated with

your design.

• Saves all edited constraints back to the XDC le from which they originated.

Note: The constraints management system preserves the original XDC les format as much as possible.

Constraints Editing Flow Options

Figure 6 shows the recommended ow opons. Do not use both opons at the same me.

Mixing these opons might cause you to lose constraints. The recommended ow opons are:

• User Interface Opon

• Hand Edit Opon

User Interface Option

Because the Vivado IDE manages your constraints, you must not edit your XDC les at the same

me. When the Vivado IDE saves the memory content, the following occurs:

• The modied constraints replace the original constraints in their original le.

• The new constraints are appended to the le marked as target.

• All manual edits in the XDC les are overwrien.

Hand Edit Option

When you use the Hand Edit opon, you are in charge of eding and maintaining the XDC les.

While you will probably use the Tcl Console to verify the syntax of some constraints, you must

discard the changes made in memory when closing or reloading your design.

In case of a conict when saving the constraints, you are prompted to choose one of the

following:

Chapter 2: Constraints Methodology

UG903 (v2022.1) June 1, 2022 www.xilinx.com

Using Constraints 19

Send Feedback

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