Lattice MachXO2 FPGA系列：超低功耗与灵活逻辑架构

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“Lattice FPGA 的 MachXO2 家族数据手册提供了关于这款低成本 FPGA 的详细规格和技术特性，包括灵活的逻辑架构、超低功耗设计、嵌入式和分布式内存、片上用户闪存以及预工程化的源同步 I/O 功能。” Lattice FPGA 的 MachXO2 家族是一款针对低成本应用而设计的现场可编程门阵列（FPGA），其数据手册（DataSheet）详细介绍了这一系列产品的各项关键特性。 1. **灵活逻辑架构**：MachXO2 系列提供六种不同规模的设备，具有从256到6864个LUT4（查找表）和19到335个输入/输出（I/O）引脚。这种灵活的架构使得设计者可以根据具体需求选择合适的器件，优化设计资源利用率。 2. **超低功耗器件**：采用先进的65nm低功耗工艺，这些器件在待机时的功率消耗可低至19微瓦。此外，它们还配备了可编程的低摆幅差分I/O，以及待机模式和其他节能选项，这使得MachXO2非常适合对功耗有严格要求的电池供电或便携式应用。 3. **嵌入式和分布式内存**：每个MachXO2器件内含最多240K比特的sysMEM™嵌入式块RAM和最多54K比特的分布式RAM。专用的FIFO控制逻辑进一步增强了内存功能，适合高速数据传输和处理。 4. **片上用户闪存**：MachXO2 提供高达256K比特的用户闪存，支持100,000次写入周期。通过WISHBONE、SPI、I2C和JTAG接口访问，用户可以将此闪存用于存储软处理器程序或作为闪存存储器。 5. **预工程化的源同步I/O**：器件内置的DDR（双倍数据速率）支持，允许高速、同步的数据传输，这对于需要高性能接口的应用，如高速串行总线和内存接口，至关重要。 6. **其他特性**：除了上述主要特点，MachXO2 还可能包含其他高级功能，如配置选项、时钟管理模块、安全特性等，这些特性使得MachXO2家族成为各种嵌入式系统和应用的理想选择，包括嵌入式控制、接口桥接、电源管理、安全加密以及系统级整合等。 Lattice FPGA 的 MachXO2 系列以其独特的低功耗、丰富的内存选项和高度灵活性，成为那些寻求性价比高、功耗敏感且功能丰富的解决方案的设计师的首选。数据手册提供了所有必要的技术细节，帮助设计者充分利用这些特性，实现高效能、低能耗的电路设计。

2-12

Architecture

MachXO2 Family Data Sheet

Figure 2-8. sysMEM Memory Primitives

Table 2-6. EBR Signal Descriptions

Port Name Description Active State

CLK Clock Rising Clock Edge

CE Clock Enable Active High

OCE

Output Clock Enable Active High

RST Reset Active High

Byte Enable Active High

WE Write Enable Active High

AD Address Bus —

DI Data In —

DO Data Out —

CS Chip Select Active High

AFF FIFO RAM Almost Full Flag —

FF FIFO RAM Full Flag —

AEF FIFO RAM Almost Empty Flag —

EF FIFO RAM Empty Flag —

RPRST FIFO RAM Read Pointer Reset —

1. Optional signals.

2. For dual port EBR primitives a trailing ‘A’ or ‘B’ in the signal name specifies the EBR port A or port B respectively.

3. For FIFO RAM mode primitive, a trailing ‘R’ or ‘W’ in the signal name specifies the FIFO read port or write port respec-

tively.

4. For FIFO RAM mode primitive FULLI has the same function as CSW(2) and EMPTYI has the same function as CSR(2).

5. In FIFO mode, CLKW is the write port clock, CSW is the write port chip select, CLKR is the read port clock, CSR is the

read port chip select, ORE is the output read enable.

DI[17:0]

CLKW

FIFO RAM

DO[17:0]

RST

FULLI

AFF

AEF

CLKR

CSR[1:0]

ORE

RPRST

CSW[1:0]

EMPTYI

ROM

DO[17:0]

AD[12:0]

CLK

RST

CS[2:0]

OCE

EBR EBR

AD[12:0]

DI[8:0]

DO[8:0]

CLK

RST

CS[2:0]

OCE

Single-Port RAM

ADA[12:0]

DIA[8:0]

CLKA

CEA

RSTA

WEA

CSA[2:0]

DOA[8:0]

OCEA

ADB[12:0]

DI[8:0]

CLKB

CEB

RSTB

WEB

CSB[2:0]

DOB[8:0]

OCEB

True Dual Port RAM

ADW[8:0]

DI[17:0]

CLKW

CEW

RST

CSW[2:0]

ADR[12:0]

CLKR

CER

DO[17:0]

CSR[2:0]

OCER

BE[1:0]

Pseudo Dual Port RAM

EBREBREBR

2-13

Architecture

MachXO2 Family Data Sheet

The EBR memory supports three forms of write behavior for single or dual port operation:

1. Normal – Data on the output appears only during the read cycle. During a write cycle, the data (at the current

address) does not appear on the output. This mode is supported for all data widths.

2. Write Through – A copy of the input data appears at the output of the same port. This mode is supported for

all data widths.

3. Read-Before-Write – When new data is being written, the old contents of the address appears at the output.

FIFO Configuration

The FIFO has a write port with data-in, CEW, WE and CLKW signals. There is a separate read port with data-out,

RCE, RE and CLKR signals. The FIFO internally generates Almost Full, Full, Almost Empty and Empty Flags. The

Full and Almost Full flags are registered with CLKW. The Empty and Almost Empty flags are registered with CLKR.

Table 2-7 shows the range of programming values for these flags.

Table 2-7. Programmable FIFO Flag Ranges

The FIFO state machine supports two types of reset signals: RST and RPRST. The RST signal is a global reset

that clears the contents of the FIFO by resetting the read/write pointer and puts the FIFO flags in their initial reset

state. The RPRST signal is used to reset the read pointer. The purpose of this reset is to retransmit the data that is

in the FIFO. In these applications it is important to keep careful track of when a packet is written into or read from

the FIFO.

Memory Core Reset

The memory core contains data output latches for ports A and B. These are simple latches that can be reset syn-

chronously or asynchronously. RSTA and RSTB are local signals, which reset the output latches associated with

port A and port B respectively. The Global Reset (GSRN) signal resets both ports. The output data latches and

associated resets for both ports are as shown in Figure 2-9.

Flag Name Programming Range

Full (FF) 1 to max (up to 2

-1)

Almost Full (AF) 1 to Full-1

Almost Empty (AE) 1 to Full-1

Empty (EF) 0

N = Address bit width.

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