2T Bandgap设计：超低功耗电压参考器

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本文档关注的是"JSSC 2-T Bandgap"，这是一项针对超低功耗电子系统设计的关键元件——2-Transistor Picowatt Temperature-compensated Voltage Reference（简称2T电压参考）。该研究发表在2012年的IEEE Journal of Solid-State Circuits上，特别关注于那些对功耗有着极严格限制的应用场景，如生物医疗植入、基础设施监控系统以及军事侦查设备，这些系统在待机状态下需消耗微弱至皮瓦特级别的功率，而在工作模式下则需达到纳瓦特水平。文章的核心创新是介绍了一种能在0.5伏特以下提供稳定电压支持的新型设计，即2T电压参考。这种设计采用了三个不同的CMOS技术进行了原型验证，展示了出色的性能。在0.13微米工艺下，该电路的温度系数最低可达16.9 ppm/°C，这是在如此低功耗下获得的优异稳定性。此外，它的线性度也相当出色，具有0.033%的每伏特变化率，这意味着即使在电压微小变化时也能保持高度精度。值得注意的是，尽管这种2T电压参考的功率消耗仅为2.22皮瓦，在1350微米²的芯片面积上实现，但它相较于其他纳米瓦特级电压参考设计，能够在保证能源效率方面提高2到3个数量级。这意味着在有限的电路面积内，它能提供更优的功耗与性能比，这对于追求极致节能的超低功耗系统设计至关重要。这项研究为设计者提供了一个在极端条件下仍能保持高精度和低功耗的电压参考解决方案，对于推动低功耗电子系统的微型化和便携化发展具有重要意义。在未来的设计中，这种2T电压参考可能被广泛应用在需要长时间运行且对能耗极其敏感的设备中，如可穿戴设备、无线传感器网络以及嵌入式系统等。

2536 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 4 7, NO. 10, OCTOBER 2012

Fig. 2. Schematic of proposed 2T voltage reference.

ture points [13], [33], [34]. Due to this ultra-low power con-

sumption, the pro posed voltage reference need no duty-cycling

for saving power, elim inating start-up issues. The design uses

subthreshold-biased devices with distinct

levels, e.g., one

regular thick oxide and one native device for achieving a stable

output voltage. As a result, the number of fabrication masks is

not increased.

Since semiconducto r process variations lead to spreads in

temperature coefﬁcient (TC) and output voltage, w e collected

statistical result s by measuring 4 9 2T voltage re fere nce proto-

types in two separate runs of 0.13

m CMOS. These exten-

sive measurement results provide a better understanding of the

advantages and limitations of the proposed design. Measure-

ment results indicate that the 2T voltage reference exhibits mod-

erate spread in TC and output voltage due t o die-to-die and

run-to-run process variations. Such process sensitivity is typi-

cally addressed through trimming. Ho wever, trimming can be

a time and cost intensive process [6]. We propose a d igitally

trimmable version of the 2T voltage reference to i mp rove TC

and output voltage accuracy across dies while enabling reason-

able trim time and cost [32]. Measurements in 0.13

mCMOS

show that the proposed trimm ing enables tight distributions of

TC and nominal output voltage across 25 dies. After one-tem -

perature point digital trimmin g, TCs lie between 13.5 ppm

and47ppm

C w h ile the nominal output voltage v aries by

0.35% from the m ean value. The typical trimmable voltage

reference consumes 29.5 pW at 0.5 V and 25

We also propose several variants of the 2T voltage reference,

including circuits to generate a speciﬁc output voltage, either

higher or lower than its nominal value. We also demonstrate

the 2T voltage referen ce with speciﬁc tem perature dependence,

PTAT o r C TAT, i n 0 .13

m CMOS. Technology portability is

also investigated. Due the wide range of supply voltage scala-

bility a nd simple top olo gy, the proposed designs often involve

only resizing o f two transistors, facilitating i ts use as an intel-

lectual property (IP) block across different technologies.

The remainder of this paper is organized as follows. Section II

introduces the design of the proposed 2T voltage reference

along with the governing eq uations for T C a n d line sensitivity

(LS). Section III describes basic measurement r esults of the

2T voltage reference in 0.13

m CMOS and compares to

previous work. Section IV investigates the impact of process

variations on the performance of the proposed 2T voltage

reference w it h additional silicon measurement results. We also

propose a assisted one temperature point trimming method,

and show that it tightens the performance spread in silicon

measurements. Section V introduces several variants of t he

2T voltage references including measured results. Section V I

demonstrates the easy port a bil ity of the 2T voltage references

by providing measurement results in tw o additional C M O S

technology nodes, while Section VII concludes the paper.

II. 2T V

OLTAGE REFERENCE DESIGN AND ANALYS IS

As mentio ned above, the use of ampliﬁers and/or saturated

MOSFETs is a key barrier to the scalability of power consump-

tion and minimum functional

in voltage references. There-

fore, we seek to eliminate them while m a int a ini n g output in-

sensitivity to temperature and supply voltage. To this end, we

propose the 2T vo ltage reference shown in Fig. 2. Two different

device types are used; in this case a native device for M1 and a

thick oxide inpu t/o utp ut (I/O) device for M2. The native device

is identical to a standard M OSFET but has a near-zero

.Both

devices have thick gate oxides to support a high

. Native de-

vices are widely available in modern foundry technologies [2 4],

[25] and do not incur additional m ask step s. One common use

of n a tiv e devices is t o limit

in thin o xide dev ices by con-

necting them in series, as shown in [26]. They have also been

used in b andg ap voltage reference circuits [8] and image sensors

[27]. Although we us e a native device for M1, any com bination

of two d evices with a considerable

difference can be used

for the 2T voltage reference. The required

difference is dis-

cussed later.

The outpu t voltage

can be modeled by (1), the well-

known subthreshold current equation where

is mobility, is

oxide capacitance, W is transistor width, L is transistor length,

m is subthreshold slope factor (

where

is depletion capacitance), is therm al voltage (kT/q), is

gate and source voltage,

is transistor threshold voltage, and

is drain to source voltag e. Setting the cu rrent through

and equal leads to (2), which holds given that 1) both de-

vices are in weak inversion, 2)

for and is greater

than 5–6

, and 3) M1 follows the subthreshold current equa-

tion at

down to . The second condition relates to the

minimum

that ensures 1% loss of accuracy given that

equals 0.982, 0.99 3, and 0.997 when is 4, 5, and

6, respectively. The third condition ensures that gate induced

drain leakage (GIDL) is not signi ﬁcan t at the operating point.

(1)

(2)

(3)

From (2), we obtain an analytical solution for

as shown

in (3), where both the ﬁrst and second terms are either pro-

portional or complemen tary to absolute temperature. Note that

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