Altera时序分析器：SDC与TimeQuest API参考手册

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"SDC_Altera.pdf - Altera公司的SDC和TimeQuest API参考手册，版本5.0" 本文档详细介绍了Altera公司的SDC（System Description Constraints）和TimeQuest时序分析器，这是一个强大的ASIC风格的时序分析工具，采用业界标准的约束、分析和报告方法来验证设计中的所有逻辑的时序性能。Altera是一家专注于可编程解决方案的公司，其产品广泛应用于全球各地。 1. SDC（System Description Constraints）： SDC是用于定义和约束FPGA或ASIC设计时序的关键工具。它允许设计师指定时钟网络、路径延迟限制、同步域跨接以及其他关键的时序约束。通过使用SDC，设计师可以确保设计满足其速度等级目标，并且能够在预期的时序环境中正确工作。 2. TimeQuest时序分析器： TimeQuest是Altera提供的一个关键设计工具，用于分析和验证设计的时序闭合。它执行详尽的时序路径分析，检查时钟路径、组合逻辑路径和寄存器到寄存器路径的延迟，以确保设计在给定的时钟周期内满足所有时序约束。此外，TimeQuest还提供了一套丰富的报告功能，帮助设计师理解和优化设计的时序性能。 3. 技术细节： TimeQuest支持多种分析功能，如最大延迟分析、最小延迟分析、路径约束分析等。它还能进行时钟树综合（CTS）、时钟偏移分析、电源电压变化的影响分析，以及针对不同工艺、电压和温度条件下的时序容差分析。 4. 版权与法律条款： Altera公司保留所有权利，其产品和服务的商标、专利、版权和面具作品权利均受法律保护。文档中提供的任何信息、产品或服务的使用，Altera不对由此产生的任何责任或损失负责，除非在书面协议中明确规定。用户应获取Altera的最新规格，以确保产品性能符合当前标准。 5. 客户支持和责任： Altera建议其客户在应用任何信息、产品或服务之前，获取最新的资料并进行适当的测试。尽管Altera的产品按照标准保修条款保证性能，但公司保留随时更改产品和服务的权利，且不承担任何因应用或使用这些信息、产品或服务而产生的责任。总结，SDC和TimeQuest是Altera设计流程中不可或缺的组成部分，它们帮助设计者确保其FPGA设计满足严格的时序要求，同时提供了强大的分析和报告功能，便于优化设计性能。了解和熟练使用这些工具对于成功完成高性能、可靠的FPGA设计至关重要。

2–6 Chapter 2: SDC and TimeQuest API Package and Commands

sdc

SDC and TimeQuest API Reference Manual © December 2009 Altera Corporation

all_registers

Usage

all_registers

Options

None

Description

Returns a collection of all regisers in the design.

Example

project_open chiptrip

create_timing_netlist

foreach_in_collection reg [all_registers] {

puts [get_register_info -name $reg]

}

report_timig -from [all_regisers] -to [all_registers]

delete_timing_netlist

project_close

Chapter 2: SDC and TimeQuest API Package and Commands 2–7

sdc

create_clock

Usage

create_clock [-add] [-name <clock_name>] -period <value> [-waveform <edge_list>]

Options

-add: Adds clock to a node with an existing clock

-name <clock_name>: Clock name of the created clock

-period <value>: Speed of the clock in terms of clock period

-waveform <edge_list>: List of edge values

<targets>: List or collection of targets

Description

Defines a clock. If the -name option is not used, the clock name is the same as the first target in the list or

collection. The clock name is used to refer to the clock in other commands.

The -period option specifies the clock period. It is also possible to use this option to specify a frequency to

define the clock period. This can be done by using -period option followed by either <frequency>MHz or

"<frequency> MHz". However, this is a TimeQuest-only extension and makes the SDC syntax

non-standard.

The -waveform option specifies the rising and falling edges (duty cycle) of the clock, and is specified as a

list of two time values: the first rising edge and the next falling edge. The rising edge must be within the

range [0, period]. The falling edge must be within one clock period of the rising edge. The waveform

defaults to (0, period/2).

If a clock with the same name is already assigned to a given target, the create_clock command will

overwrite the existing clock. If a clock with a different name exists on the given target, the create_clock

command will be ignored unless the -add option is used. The -add option can be used to assign multiple

clocks to a pin or port.

If the target of the clock is internal (i.e. not an input port), the source latency is zero by default.

If a clock is on a path after another clock, then it blocks or overwrites the previous clock from that point

forward.

The value of the targets is either a collection or a Tcl list of wildcards used to create a collection of the

appropriate type. The values used must follow standard Tcl or TimeQuest-extension substitution rules.

See the help for use_timequest_style_escaping for details.

Example

# Create a simple 10ns with clock with a 60% duty cycle

create_clock -period 10 -waveform {0 6} -name clk [get_ports clk]

# Create a clock with a falling edge at 2ns, rising edge at 8ns,

# falling at 12ns, etc.

create_clock -period 10 -waveform {8 12} -name clk [get_ports clk]

# Assign two clocks to an input port that are switched externally

create_clock -period 10 -name clk100Mhz [get_ports clk]

create_clock -period 6.667 -name clk150Mhz -add [get_ports clk]

# Two ways to use MHz to define clock period (TimeQuest only)

create_clock -period 250MHz -name clk250MHz [get_ports clk]

create_clock -period "250 MHz" -name clk250MHz [get_ports clk]

2–8 Chapter 2: SDC and TimeQuest API Package and Commands

sdc

SDC and TimeQuest API Reference Manual © December 2009 Altera Corporation

create_generated_clock

Usage

create_generated_clock [-add] [-divide_by <factor>] [-duty_cycle <percent>]

[-edge_shift <shift_list>] [-edges <edge_list>] [-invert] [-master_clock <clock>]

[-multiply_by <factor>] [-name <clock_name>] [-offset <time>] [-phase <degrees>]

-source <clock_source> <targets>

Options

-add: Add clock to existing clock node

-divide_by <factor>: Division factor

-duty_cycle <percent>: Specifies the duty cycle as a percentage of the clock

period--accepts floating point values

-edge_shift <shift_list>: List of edge shifts

-edges <edge_list>: List of edge values

-invert: Invert the clock waveform

-master_clock <clock>: Specifies clock of the source node

-multiply_by <factor>: Multiplication factor

-name <clock_name>: Name of generated clock

-offset <time>: Specifies the offset as an absolute time shift

-phase <degrees>: Specifies the phase shift in degrees

-source <clock_source>: Source node for the generated clock

<targets>: List or collection of targets

Description

Defines an internally generated clock. If -name is not specified, the clock name is the same as the first

target in the list or collection. The clock name is used to refer to the clock in other commands.

If a clock with the same name is already assigned to a given target, the create_generated_clock command

will overwrite the existing clock. If a clock with a different name exists on the given target, the

create_generated_clockcommand will be ignored unless the -add option is used. The -add option can be

used to assign multiple clocks to a pin or port, and is recommended be used with -master_clock option.

The source of the generated clock, specified by -source, is a port, pin, register, or net in the design. All

waveform modifications are relative to this point. If more than one clock feeds the source node, the

-master_clock option must be used to specify which clock to modify.

The source latency of the generated clock is based on the clock network of the generated clock, and not the

clock network of the node specified using -source. This latency is added to any source latency of the

master clock.

The -divide_by, -multiply_by, -invert, -duty_cycle, -edges, and -edge_shift options modify the waveform

relative to the waveform at the source node.

Clock division and multiplication, using -divide_by and -multiply_by, is performed relative to the first

rising edge. Clock division is based on edges in the master clock waveform, and scaled if the division is an

odd number. Use the -duty_cycle option to specify the new duty cycle for clock multiplication. Use the

-phase option to specify any phase shift relative to the new clock period. Use the -offset option to specify

an arbitrary offset or time shift. Use the -invert option to invert the waveform.

Chapter 2: SDC and TimeQuest API Package and Commands 2–9

sdc

Clock generation can also be specified with the -edges and -edge_shift options. The -edges option accepts a

list of three numbers specifying the master clock edges to use for the first rising edge, the next falling edge,

and next rising edge. Edges of the master clock are labeled according to the first rising edge (1), next falling

edge (2), next rising edge (3), etc. For example, a basic clock divider can be specified equivalently with

-divide_by 2 or -edges {1 3 5}. The -edge_shift option accepts a list of three time values, the amount to shift

each of the three edges.

The value of the targets is either a collection or a Tcl list of wildcards used to create a collection of the

appropriate type. The values used must follow standard Tcl or TimeQuest-extension substitution rules.

See the help for use_timequest_style_escaping for details.

Example

# Create a clock and a divide-by-2 generated clock

create_clock -period 10 [get_ports clk]

create_generated_clock -divide_by 2 -source [get_ports clk] -name clkdiv \

[get_registers clkdiv]

# An equivalent generated clock

create_generated_clock -edges {1 3 5} -source [get_ports clk] -name \

clkdiv [get_registers clkdiv]

# Specify a clock multipler with a 60% duty cycle

create_generated_clock -multiply_by 2 -duty_cycle 60 \

[get_pins clkmult|combout]

# Specify an inverted divide-by-2 clock relative to the output of the

# source clock

create_generated_clock -divide_by 2 -invert -source [get_ports clk] -name \

nclkdiv [get_registers clkdiv]

# Specify a divide-by-2 clock with a 90-degree phase shift

create_generated_clock -divide_by 2 -phase 90 -source [get_ports clk] \

-name clkdiv [get_registers clkdiv]

# Assign two clocks to an input port that are switched externally,

# along with an internal clock divider.

create_clock -period 10 -name clk100Mhz [get_ports clk]

create_clock -period 6.667 -name clk150Mhz -add [get_ports clk]

create_generated_clock -divide_by 2 -name clk50Mhz -source [get_ports \

clk] -master_clock clk100Mhz -add [get_registers clkdiv]

create_generated_clock -divide_by 2 -name clk75Mhz -source [get_ports \

clk] -master_clock clk150Mhz -add [get_registers clkdiv]

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