"ARM发布AMBA 5 CHI协议最新release版本"

需积分: 23 18 浏览量更新于2023-12-27 1 收藏 2.7MB PDF 举报

The IHI0050F-amba-5-chi-architecture-spec is the latest release version of the CHI protocol. The copyright for this specification belongs to Arm Limited or its affiliates, and all rights are reserved. This document, with the non-confidential ID092622, outlines the AMBA® 5 CHI Architecture Specification and is copyright protected by Arm Limited or its affiliates. The Release Information Change history section of the document lists the alterations made to this specification, providing a comprehensive record of modifications. Additionally, the document contains a proprietary notice stating that it is non-confidential and open for use. In conclusion, the IHI0050F-amba-5-chi-architecture-spec is a detailed and comprehensive specification of the CHI protocol, providing valuable information for those seeking to understand and utilize this technology. With its non-confidential status and copyright protection, it serves as an important resource for interested parties in the industry.

Preface

About this specification

Non-Confidential ID092622

Signals

The signal conventions are:

Signal level The level of an asserted signal depends on whether the signal is active-HIGH or

active-LOW. Asserted means:

• HIGH for active-HIGH signals.

• LOW for active-LOW signals.

Lowercase n At the start or end of a signal name denotes an active-LOW signal.

Numbers

Numbers are normally written in decimal. Binary numbers are preceded by

, and hexadecimal numbers by

Both are written in a

monospace

font.

Additional reading

This section lists relevant publications from Arm.

See Arm Developer

https://developer.arm.com/documentation

, for access to Arm documentation.

Arm publications

• AMBA

AXI and ACE Protocol Specification (ARM IHI 0022).

Introduction

1.1 Architecture overview

Non-Confidential ID092622

1.1 Architecture overview

The CHI architecture is a scalable, coherent hub interface and on-chip interconnect used by multiple

components.The CHI architecture allows for flexible topologies of component connections, driven by performance,

power, and area system requirements.

1.1.1 Components

The components of CHI-based systems can comprise of:

• Standalone processors

• Processor clusters

• Graphic processors

• Memory controllers

• I/O bridges

• PCIe subsystems

• Interconnects

1.1.2 Key features

The key features of the architecture are:

• Scalable architecture, enabling modular designs that scale from small to large systems.

• Independent layered approach, comprising of Protocol, Network, and Link layer, with distinct functionalities.

• Packet-based communication.

• All transactions handled by an interconnect-based Home Node that co-ordinates required snoops, cache, and

memory accesses.

• The CHI coherence protocol supports:

— Coherency granule of 64-byte cache line.

— Snoop filter and directory-based systems for snoop scaling.

— Both MESI and MOESI cache models with forwarding of data from any cache state.

— Additional partial and empty cache line states.

• The CHI transaction set includes:

— Enriched transaction types that permit performance, area, and power efficient system cache

implementation.

— Support for atomic operations and synchronization within the interconnect.

— Support for the efficient execution of Exclusive accesses.

— Transactions for the efficient movement and placement of data, to move data in a timely manner closer

to the point of anticipated use.

— Virtual memory management through Distributed Virtual Memory (DVM) operations.

• Request retry to manage protocol resources.

• Support for end-to-end Quality of Service (QoS).

• Support for the Arm Memory Tagging Extension (MTE).

• Support for the Arm Realm Management Extension (RME).

• Configurable data width to meet the requirements of the system.

• ARM TrustZone

™

support on a transaction-by-transaction basis.

• Optimized transaction flow for coherent writes with a producer-consumer ordering model.

剩余527页未读，继续阅读

健忘的过去

粉丝: 1
资源: 20

"ARM发布AMBA 5 CHI协议最新release版本"

AMBA 5 CHI Architecture Specification.pdf

AMBA5-IHI0050E-AMBA 5 CHI Architecture Specification

IHI0050D_amba_5_chi_architecture_spec.pdf

IHI0050E-b-amba-5-chi-architecture-spec

IHI0050E-c-amba-chi-architecture-spec

IHI0068D-amba-low-power-interface-spec

IHI0022J-amba-axi-protocol-spec.pdf

IHI0022E-amba-axi-and-ace-protocol-spec

IHI0022C-amba-axi-v2-0

AMBA5-IHI0032C-AMBA ATB Protocol Specification

最新资源