ARM7微控制器LPC2101_02_03用户手册

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"LPC2101_02_03 用户手册(英) - LPC2101系列微控制器的用户手册，由Philips Semiconductors发布，详细介绍了这些基于ARM7TDMI-SCPU的32位嵌入式微控制器，包括其特性、功能和使用方法。" 本文档是Philips Semiconductors发布的LPC2101、LPC2102和LPC2103微控制器的初步用户手册，修订版本为01，发布日期为2006年1月12日。手册涵盖了这些微控制器的基础信息，关键词包括LPC2101、LPC2102、LPC2103、ARM架构、嵌入式系统和32位微控制器。 LPC2101/02/03系列微控制器的核心是16位/32位ARM7TDMI-S处理器，支持实时仿真，集成了不同容量（8KB、16KB或32KB）的高速嵌入式闪存。其独特的128位宽内存接口和加速器架构使得32位代码能够在高效率下执行。这些特性使得该系列微控制器适用于需要高效能和紧凑存储空间的嵌入式应用。手册详细介绍了微控制器的主要特点，可能包括但不限于以下内容： 1. 内部结构：ARM7TDMI-S内核的详细说明，包括指令集、中断处理和调试选项。 2. 存储系统：高速闪存的工作机制，以及可能的扩展存储选项。 3. 外设接口：如I/O端口、定时器、串行通信接口（UART）、SPI、I2C等。 4. 模拟功能：可能包括ADC（模拟数字转换器）、DAC（数字模拟转换器）和其他模拟接口。 5. 电源管理：低功耗模式和电源控制选项。 6. 系统时钟：时钟源、分频器和时钟管理系统。 7. 片上调试支持：可能包括JTAG接口和其他调试工具的使用说明。 8. 应用示例和开发工具：如何使用这些微控制器进行项目开发，可能包含示例代码和开发环境的配置指南。此外，手册还提供了联系方式，用户可以通过访问Philips Semiconductors的官方网站或者发送邮件获取更多信息和支持。修订历史部分记录了手册的更新情况，此版本为初始版本。通过这份用户手册，开发者可以深入了解LPC2101/02/03系列微控制器的各个方面，从而有效地设计和实现基于这些微控制器的嵌入式系统。无论是初学者还是经验丰富的工程师，都能从中受益，掌握如何利用这些微控制器的强大功能来满足各种项目需求。

User manual Rev. 01 — 12 January 2006 16

Philips Semiconductors

UM10161

Volume 1 Chapter 3: System control block

3.3 Register description

All registers, regardless of size, are on word address boundaries. Details of the registers

appear in the description of each function.

[1] Reset value reflects the data stored in used bits only. It does not include reserved bits content.

3.4 Crystal oscillator

The LPC2101/02/03 onboard oscillator circuit supports external crystals in the range of

1 MHz to 25 MHz only. If the on-chip PLL system or the boot-loader is used, the input

clock frequency is limited to an exclusive range of 10 MHz to 25 MHz.

The oscillator output frequency is called F

OSC

and the ARM processor clock frequency is

referred to as CCLK for purposes of rate equations, etc. elsewhere in this document. F

OSC

and CCLK are the same value unless the PLL is running and connected. Refer to the

Section 3.8 “

Phase Locked Loop (PLL)” on page 24 for details and frequency limitations.

The onboard oscillator in the LPC2101/02/03 can operate in one of two modes: slave

mode and oscillation mode.

Table 6: Summary of system control registers

Name Description Access Reset

value

[1]

Address

External Interrupts

EXTINT External Interrupt Flag Register R/W 0 0xE01F C140

INTWAKE Interrupt Wake-up Register R/W 0 0xE01F C144

EXTMODE External Interrupt Mode Register R/W 0 0xE01F C148

EXTPOLAR External Interrupt Polarity Register R/W 0 0xE01F C14C

Memory Mapping Control

MEMMAP Memory Mapping Control R/W 0 0xE01F C040

Phase Locked Loop

PLLCON PLL Control Register R/W 0 0xE01F C080

PLLCFG PLL Configuration Register R/W 0 0xE01F C084

PLLSTAT PLL Status Register RO 0 0xE01F C088

PLLFEED PLL Feed Register WO NA 0xE01F C08C

Power Control

PCON Power Control Register R/W 0 0xE01F C0C0

PCONP Power Control for Peripherals R/W 0x03BE 0xE01F C0C4

APB Divider

APBDIV APB Divider Control R/W 0 0xE01F C100

Reset

RSIR Reset Source Identification Register R/W 0 0xE01F C180

Code Security/Debugging

CSPR Code Security Protection Register RO 0 0xE01F C184

Syscon Miscellaneous Registers

SCS System Controls and Status R/W 0 0xE01F C1A0

User manual Rev. 01 — 12 January 2006 19

Philips Semiconductors

UM10161

Volume 1 Chapter 3: System control block

3.5.1 Register description

The external interrupt function has four registers associated with it. The EXTINT register

contains the interrupt flags and the EXTWAKE register contains bits that enable individual

external interrupts to wake up the microcontroller from Power-down mode. The

EXTMODE and EXTPOLAR registers specify the level and edge sensitivity parameters.

[1] Reset value reflects the data stored in used bits only. It does not include reserved bits content.

3.5.2 External Interrupt Flag register (EXTINT - 0xE01F C140)

When a pin is selected for its external interrupt function, the level or edge on that pin

(selected by its bits in the EXTPOLAR and EXTMODE registers) will set its interrupt flag in

this register. This asserts the corresponding interrupt request to the VIC, which will cause

an interrupt if interrupts from the pin are enabled.

Writing ones to bits EINT0 through EINT2 in EXTINT register clears the corresponding

bits. In level-sensitive mode this action is efficacious only when the pin is in its inactive

state.

Once a bit from EINT0 to EINT2 is set and an appropriate code starts to execute (handling

wake-up and/or external interrupt), this bit in EXTINT register must be cleared. Otherwise

the event that was just triggered by activity on the EINT pin will not be recognized in the

future.

Important: whenever a change of external interrupt operating mode (i.e. active

level/edge) is performed (including the initialization of an external interrupt), the

corresponding bit in the EXTINT register must be cleared! For details see Section

3.5.4 “External Interrupt Mode register (EXTMODE - 0xE01F C148)” and Section 3.5.5

“External Interrupt Polarity register (EXTPOLAR - 0xE01F C14C)”.

For example, if a system wakes up from power-down using a LOW level on external

interrupt 0 pin, its post-wake-up code must reset the EINT0 bit in order to allow future

entry into the power-down mode. If the EINT0 bit is left set to 1, subsequent attempt(s) to

invoke power-down mode will fail. The same goes for external interrupt handling.

More details on power-down mode will be discussed in the following chapters.

Table 8: External interrupt registers

Name Description Access Reset

value

[1]

Address

EXTINT The External Interrupt Flag Register contains

interrupt flags for EINT0, EINT1, EINT2 and

EINT3. See Tab le 9

R/W 0 0xE01F C140

EXTWAKE The Interrupt wake-up register contains four

enable bits that control whether each external

interrupt will cause the processor to wake up

from Power-down mode. See Ta ble 10

R/W 0 0xE01F C144

EXTMODE The External Interrupt Mode Register controls

whether each pin is edge- or level sensitive.

R/W 0 0xE01F C148

EXTPOLAR The External Interrupt Polarity Register controls

which level or edge on each pin will cause an

interrupt.

R/W 0 0xE01F C14C

User manual Rev. 01 — 12 January 2006 20

Philips Semiconductors

UM10161

Volume 1 Chapter 3: System control block

3.5.3 Interrupt Wake-up register (INTWAKE - 0xE01F C144)

Enable bits in the INTWAKE register allow the external interrupts and other sources to

wake up the processor if it is in Power-down mode. The related EINTn function must be

mapped to the pin in order for the wake-up process to take place. It is not necessary for

the interrupt to be enabled in the Vectored Interrupt Controller for a wake-up to take place.

This arrangement allows additional capabilities, such as having an external interrupt input

wake up the processor from Power-down mode without causing an interrupt (simply

resuming operation), or allowing an interrupt to be enabled during Power-down without

waking the processor up if it is asserted (eliminating the need to disable the interrupt if the

wake-up feature is not desirable in the application).

For an external interrupt pin to be a source that would wake up the microcontroller from

Power-down mode, it is also necessary to clear the corresponding bit in the External

Interrupt Flag register (see Section 3.5.2 on page 19

Table 9: External Interrupt Flag register (EXTINT - address 0xE01F C140) bit description

Bit Symbol Description Reset

value

0 EINT0 In level-sensitive mode, this bit is set if the EINT0 function is selected for its pin, and the pin is in

its active state. In edge-sensitive mode, this bit is set if the EINT0 function is selected for its pin,

and the selected edge occurs on the pin.

This bit is cleared by writing a one to it, except in level sensitive mode when the pin is in its active

state (e.g. if EINT0 is selected to be LOW level sensitive and a LOW level is present on the

corresponding pin, this bit can not be cleared; this bit can be cleared only when the signal on the

pin becomes HIGH).

1 EINT1 In level-sensitive mode, this bit is set if the EINT1 function is selected for its pin, and the pin is in

its active state. In edge-sensitive mode, this bit is set if the EINT1 function is selected for its pin,

and the selected edge occurs on the pin.

This bit is cleared by writing a one to it, except in level sensitive mode when the pin is in its active

state (e.g. if EINT1 is selected to be LOW level sensitive and a LOW level is present on the

corresponding pin, this bit can not be cleared; this bit can be cleared only when the signal on the

pin becomes HIGH).

2 EINT2 In level-sensitive mode, this bit is set if the EINT2 function is selected for its pin, and the pin is in

its active state. In edge-sensitive mode, this bit is set if the EINT2 function is selected for its pin,

and the selected edge occurs on the pin.

This bit is cleared by writing a one to it, except in level sensitive mode when the pin is in its active

state (e.g. if EINT2 is selected to be LOW level sensitive and a LOW level is present on the

corresponding pin, this bit can not be cleared; this bit can be cleared only when the signal on the

pin becomes HIGH).

7:3 - Reserved, user software should not write ones to reserved bits. The value read from a reserved

bit is not defined.

Table 10: Interrupt Wake-up register (INTWAKE - address 0xE01F C144) bit description

Bit Symbol Description Reset

value

0 EXTWAKE0 When one, assertion of EINT0 will wake up the processor from

Power-down mode.

1 EXTWAKE1 When one, assertion of EINT1 will wake up the processor from

Power-down mode.

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