1.35V DDR3L SDRAM MT41K256M8DA-125规格书：低电压汽车级内存详解

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本文档是一份关于2GB DDR3L SDRAM MT41K256M8DA-125 AIT规格书，它详细介绍了针对汽车应用设计的1.35V DDR3L SDRAM模块。该设备是DDR3 SDRAM的低电压版本，旨在在1.5V兼容模式下运行时遵循DDR3的标准规格。以下是文档中的关键知识点： 1. **工作电压**：DDR3L工作在1.35V（1.283V至1.45V）的低电压范围内，同时兼容1.5V DDR3 SDRAM，支持在两种电压下的操作，提供了更大的灵活性。 2. **数据传输**：采用差分双向数据 strobe 功能，保证了数据传输的可靠性，同时有8n位预取架构，提高数据访问速度。 3. **接口特性**：设备配备差分时钟输入（CK和CK#），具有8个内部银行，支持动态确定数据、strobes和mask信号的读写操作。 4. **延迟控制**：允许编程CAS（读取）延迟（CL）、POSTED CAS附加延迟（AL）以及CAS（写入）延迟（CWL）。固定突发长度（BL）为8，且通过模制寄存器集（MRS）支持突发切片（BC）4的动态选择，进一步提升性能。 5. **电源管理**：提供自刷新模式，允许在不同温度范围内设置刷新间隔时间，如-64ms到+125°C范围内，确保长时间稳定运行。此外，还包含自动自刷新（ASR）功能，适应不同应用场景需求。 6. **内存优化**：内置写平滑功能，有助于减少写操作对内存的影响，提高整体效率。多用途寄存器提供额外的配置选项。 7. **输出驱动校准**：为了确保最佳信号质量，输出驱动器进行了优化校准，以适应不同负载和系统环境。这份规格书对于理解和设计使用DDR3L SDRAM模块的系统工程师来说非常有价值，无论是为了实现低功耗设计还是满足特定温度范围内的性能要求，都能从中获取关键参数和功能细节。设计师可以通过查阅这些参数，确保他们的系统能够在1.35V DDR3L规范下正常工作并达到预期性能。

Ball Assignments and Descriptions

Figure 5: 78-Ball FBGA – x8 Ball Assignments (Top View)

1234 67895

DDQ

SSQ

REFDQ

ODT

SSQ

DQ2

DQ6

DDQ

CS#

BA0

RESET#

DQ0

DQS

DQS#

DQ4

RAS#

CAS#

WE#

BA2

A13

NF/TDQS#

DM/TDQS

DQ1

DQ7

CK#

A10/AP

A15

A12/BC#

A11

A14

DDQ

SSQ

DDQ

CKE

SSQ

DQ3

DQ5

REFCA

BA1

Note:

1. A comma separates the configuration; a slash defines a selectable function—selectable

between NF or TDQS# via MRS (symbols are defined in Table 3).

2Gb: x8, x16 Automotive DDR3L SDRAM

Ball Assignments and Descriptions

09005aef85741711

2Gb_auto_DDR3L.pdf - Rev. B 6/16 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

Table 3: 78-Ball FBGA – x8 Ball Descriptions

Symbol Type Description

A[14:13],

A12/BC#, A11,

A10/AP,

A[9:0]

Input Address inputs: Provide the row address for ACTIVATE commands, and the column ad-

dress and auto precharge bit (A10) for READ/WRITE commands, to select one location out

of the memory array in the respective bank. A10 sampled during a PRECHARGE com-

mand determines whether the PRECHARGE applies to one bank (A10 LOW, bank selected

by BA[2:0]) or all banks (A10 HIGH). The address inputs also provide the op-code during a

LOAD MODE command. Address inputs are referenced to V

REFCA

. A12/BC#: When enabled

in the mode register (MR), A12 is sampled during READ and WRITE commands to deter-

mine whether burst chop (on-the-fly) will be performed (HIGH = BL8 or no burst chop,

LOW = BC4 burst chop). See Truth Table - Command.

BA[2:0] Input Bank address inputs: BA[2:0] define the bank to which an ACTIVATE, READ, WRITE, or

PRECHARGE command is being applied. BA[2:0] define which mode register (MR0, MR1,

MR2, or MR3) is loaded during the LOAD MODE command. BA[2:0] are referenced to

REFCA

CK, CK# Input Clock: CK and CK# are differential clock inputs. All address and control input signals are

sampled on the crossing of the positive edge of CK and the negative edge of CK#. Out-

put data strobe (DQS, DQS#) is referenced to the crossings of CK and CK#.

CKE Input Clock enable: CKE enables (registered HIGH) and disables (registered LOW) internal cir-

cuitry and clocks on the DRAM. The specific circuitry that is enabled/disabled is depend-

ent upon the DDR3 SDRAM configuration and operating mode. Taking CKE LOW pro-

vides PRECHARGE power-down and SELF REFRESH operations (all banks idle) or active

power-down (row active in any bank). CKE is synchronous for power-down entry and exit

and for self refresh entry. CKE is asynchronous for self refresh exit. Input buffers (exclud-

ing CK, CK#, CKE, RESET#, and ODT) are disabled during power-down. Input buffers (ex-

cluding CKE and RESET#) are disabled during SELF REFRESH. CKE is referenced to

REFCA

CS# Input Chip select: CS# enables (registered LOW) and disables (registered HIGH) the command

decoder. All commands are masked when CS# is registered HIGH. CS# provides for exter-

nal rank selection on systems with multiple ranks. CS# is considered part of the command

code. CS# is referenced to V

REFCA

DM Input Input data mask: DM is an input mask signal for write data. Input data is masked when

DM is sampled HIGH along with the input data during a write access. Although the DM

ball is input-only, the DM loading is designed to match that of the DQ and DQS balls. DM

is referenced to V

REFDQ

. DM has an optional use as TDQS on the x8 device.

ODT Input On-die termination: ODT enables (registered HIGH) and disables (registered LOW) ter-

mination resistance internal to the DDR3 SDRAM. When enabled in normal operation,

ODT is only applied to each of the following balls: DQ[7:0], DQS, DQS#, and DM for the

x8. The ODT input is ignored if disabled via the LOAD MODE command. ODT is refer-

enced to V

REFCA

RAS#, CAS#, WE# Input Command inputs: RAS#, CAS#, and WE# (along with CS#) define the command being

entered and are referenced to V

REFCA

RESET# Input Reset: RESET# is an active LOW CMOS input referenced to V

. The RESET# input receiver

is a CMOS input defined as a rail-to-rail signal with DC HIGH ≥ 0.8 × V

DDQ

and DC LOW ≤

0.2 × V

DDQ

. RESET# assertion and deassertion are asynchronous.

DQ[7:0] I/O Data input/output: Bidirectional data bus for the x8 configuration. DQ[7:0] are refer-

enced to V

REFDQ

2Gb: x8, x16 Automotive DDR3L SDRAM

Ball Assignments and Descriptions

09005aef85741711

2Gb_auto_DDR3L.pdf - Rev. B 6/16 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

Table 4: 96-Ball FBGA – x16 Ball Descriptions

Symbol Type Description

A13, A12/BC#,

A11, A10/AP,

A[9:0]

Input Address inputs: Provide the row address for ACTIVATE commands, and the column ad-

dress and auto precharge bit (A10) for READ/WRITE commands, to select one location out

of the memory array in the respective bank. A10 sampled during a PRECHARGE com-

mand determines whether the PRECHARGE applies to one bank (A10 LOW, bank selected

by BA[2:0]) or all banks (A10 HIGH). The address inputs also provide the op-code during a

LOAD MODE command. Address inputs are referenced to V

REFCA

. A12/BC#: When enabled

in the mode register (MR), A12 is sampled during READ and WRITE commands to deter-

mine whether burst chop (on-the-fly) will be performed (HIGH = BL8 or no burst chop,

LOW = BC4 burst chop). See Truth Table - Command.

BA[2:0] Input Bank address inputs: BA[2:0] define the bank to which an ACTIVATE, READ, WRITE, or

PRECHARGE command is being applied. BA[2:0] define which mode register (MR0, MR1,

MR2, or MR3) is loaded during the LOAD MODE command. BA[2:0] are referenced to

REFCA

CK, CK# Input Clock: CK and CK# are differential clock inputs. All address and control input signals are

sampled on the crossing of the positive edge of CK and the negative edge of CK#. Out-

put data strobe (LDQS, LDQS#, UDQS, UDQS#) is referenced to the crossings of CK and

CK#.