AMD Am29LV800B：8兆位CMOS 3.0伏单电源Boot Sector Flash内存

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"AM29LV800B是一款8兆位（1Mx8位/512Kx16位）的CMOS3.0伏特仅电压启动扇区闪存内存。此数据手册提供了AMD关于该产品的当前技术规格。" 在了解AM29LV800B芯片之前，我们首先需要知道它是一款闪存存储器，主要用于存储数据并在断电后仍能保持数据不丢失。这款芯片的关键特性包括： 1. **单一电源操作**：AM29LV800B可在2.7到3.6伏特的电压范围内进行读写操作，非常适合电池供电的应用，确保了在低电压环境下的正常工作。 2. **0.32微米工艺技术**：采用先进的0.32微米工艺制造，与0.5微米的AM29LV800设备兼容，这意味着更高的集成度和更低的功耗。 3. **高性能**：该芯片具有快速的访问时间，最快可达到70纳秒，确保了高速的数据存取能力。 4. **超低功耗**：在5MHz工作频率下，典型值包括200nA的自动睡眠模式电流、200nA的待机模式电流以及7mA的读取电流和15mA的编程/擦除电流。这显著降低了运行时的能耗。 5. **灵活的扇区架构**：AM29LV800B有多种大小的扇区，包括1个16K字节、2个8K字节、1个32K字节和15个64K字节的扇区（按字节模式），以及1个8K字、2个4K字、1个16K字和15个32K字的扇区（按字模式）。这种设计允许对数据进行灵活的分区和管理。 6. **整片擦除支持**：支持整个芯片的擦除操作，方便进行大范围的数据清除。 7. **扇区保护功能**：提供硬件方法锁定扇区，防止任何未经授权的编程或擦除操作，增强了数据的安全性。 8. **编程/擦除操作**：尽管未详细说明编程和擦除的具体时间，但根据其规格，这些操作应该比传统的EPROM更快，且具有较高的耐久性。 AM29LV800B是一款适用于嵌入式系统、电池驱动设备和需要高速、低功耗和安全存储解决方案的场合的先进闪存芯片。其灵活的扇区结构和保护功能使其成为嵌入式系统设计中的理想选择。数据手册的详细内容会进一步提供编程接口、时序图、电气特性、封装信息以及更多关于如何正确使用和控制该芯片的指导。

8 Am29LV800B

ORDERING INFORMATION

Standard Products

AMD standard products are available in several packages and operating ranges. The order number (Valid Combi-

nation) is formed by a combination of the elements below.

Valid Combinations

Valid Combinations list configurations planned to be sup-

ported in volume for this device. Consult the local AMD sales

office to confirm availability of specific valid combinations and

to check on newly released combinations.

Am29LV800B T -70 E C

TEMPERATURE RANGE

C=Commercial (0°C to +70°C)

I = Industrial (–40

°C to +85°C)

E = Extended (–55

°C to +125°C)

PACKAGE TYPE

E = 48-Pin Thin Small Outline Package (TSOP) Standard Pinout (TS 048)

F = 48-Pin Thin Small Outline Package (TSOP) Reverse Pinout (TSR048)

S = 44-Pin Small Outline Package (SO 044)

WB = 48-Ball Fine Pitch Ball Grid Array (FBGA)

0.80 mm pitch, 6 x 9 mm package (FBB048)

This device is also available in Known Good Die (KGD) form. See publication number

21536 for more information.

SPEED OPTION

See Product Selector Guide and Valid Combinations

BOOT CODE SECTOR ARCHITECTURE

T = Top sector

B = Bottom sector

DEVICE NUMBER/DESCRIPTION

Am29LV800B

8 Megabit (1 M x 8-Bit/512 K x 16-Bit) CMOS Flash Memory

3.0 Volt-only Read, Program, and Erase

Valid Combinations for TSOP and SO Packages

AM29LV800BT-70,

AM29LV800BB-70

EC, EI, FC, FI, SC, SI

AM29LV800BT-90,

AM29LV800BB-90

EC, EI, EE,

FC, FI, FE,

SC, SI, SE

AM29LV800BT-120,

AM29LV800BB-120

Valid Combinations for FBGA Packages

Order Number Package Marking

AM29LV800BT-70,

AM29LV800BB-70

WBC,

WBI

L800BT70V,

L800BB70V

C, I

AM29LV800BT-90,

AM29LV800BB-90

L800BT90V,

L800BB90V

AM29LV800BT-120,

AM29LV800BB-120

L800BT12V,

L800BB12V

Am29LV800B 9

DEVICE BUS OPERATIONS

This section describes the requirements and use of the

device bus operations, which are initiated through the

internal command register. The command register

itself does not occupy any addressable memory loca-

tion. The register is composed of latches that store the

commands, along with the address and data informa-

tion needed to execute the command. The contents of

the register serve as inputs to the internal state

machine. The state machine outputs dictate the func-

tion of the device. Table 1 lists the device bus opera-

tions, the inputs and control levels they require, and the

resulting output. The following subsections describe

each of these operations in further detail.

Table 1. Am29LV800B Device Bus Operations

Legend:

L = Logic Low = V

, H = Logic High = V

, V

= 12.0

0.5 V, X = Don’t Care, A

= Address In, D

= Data In, D

OUT

= Data Out

Notes:

1. Addresses are A18:A0 in word mode (BYTE# = V

), A18:A-1 in byte mode (BYTE# = V

2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector

Protection/Unprotection” section.

Word/Byte Configuration

The BYTE# pin controls whether the device data I/O

pins DQ15–DQ0 operate in the byte or word configura-

tion. If the BYTE# pin is set at logic ‘1’, the device is in

word configuration, DQ15–DQ0 are active and con-

trolled by CE# and OE#.

If the BYTE# pin is set at logic ‘0’, the device is in byte

configuration, and only data I/O pins DQ0–DQ7 are ac-

tive and controlled by CE# and OE#. The data I/O pins

DQ8–DQ14 are tri-stated, and the DQ15 pin is used as

an input for the LSB (A-1) address function.

Requirements for Reading Array Data

To read array data from the outputs, the system must

drive the CE# and OE# pins to V

. CE# is the power

control and selects the device. OE# is the output con-

trol and gates array data to the output pins. WE# should

remain at V

. The BYTE# pin determines whether the

device outputs array data in words or bytes.

The internal state machine is set for reading array

data upon device power-up, or after a hardware reset.

This ensures that no spurious alteration of the mem-

ory content occurs during the power transition. No

command is necessary in this mode to obtain array

data. Standard microprocessor read cycles that as-

sert valid addresses on the device address inputs pro-

duce valid data on the device data outputs. The device

remains enabled for read access until the command

See “Reading Array Data” for more information. Refer

to the AC Read Operations table for timing specifica-

tions and to Figure 13 for the timing diagram. I

CC1

the DC Characteristics table represents the active cur-

rent specification for reading array data.

Writing Commands/Command Sequences

To write a command or command sequence (which in-

cludes programming data to the device and erasing

Operation CE# OE# WE# RESET#

Addresses

(Note 1)

DQ0–

DQ7

DQ8–DQ15

BYTE#

= V

BYTE#

= V

Read L L H H A

OUT

DQ8–DQ14 = High-Z,

DQ15 = A-1

Write L H L H A

Standby

0.3 V

X High-Z High-Z High-Z

Output Disable L H H H X High-Z High-Z High-Z

Reset X X X L X High-Z High-Z High-Z

Sector Protect (Note 2) L H L V

Sector Address,

A6 = L, A1 = H,

A0 = L

Sector Unprotect (Note 2) L H L V

Sector Address,

A6 = H, A1 = H,

A0 = L

Temporary Sector Unprotect X X X V

High-Z

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