memory implementations [3, 7, 12, 13] because transactions can fail when the work-
ing set exceeds the capacity of the underlying hardware. The capacity constraints
that dictate the conditions under which these failures inevitably occur dramatically
influence whether the complexity of designing a software system using restricted HTM
is justified by the expected performance.
The feasibility tradeoff imposed by the capacity constraints is just one considera-
tion in the design of software systems using restricted HTM. If the ultimate goal is
to build fast concurrent programs, then we must also focus our attention on finding
the optimal use cases for HTM. This motivation leads us to explore the design space
of multicore programs to understand how hardware transactions perform in different
cases of contention.
Our goal in this paper is to characterize the capacity constraints of HTM and to
discover their performance characteristics with respect to contention parameters like
transaction size or write ratio. These are the steps we have taken to move closer to
this end:
∙ Empirically study the capacity constraints of hardware transactions to expose
the hardware implementations that dictate these limits
∙ Articulate a set of contention parameters, like transaction size or write ratio,
that sufficiently span the multicore design space and can be used to synthetically
generate different cases of contention for benchmarking
∙ Discover performance trends of hardware transactions with respect to different
contention parameters
∙ Capture these trends in a multivariate linear regression model that can be used
to predict HTM performance in real multicore programs
We anticipate these contributions will provide a much needed understanding of
hardware transactional memory to better enable its effective utilization in future
multicore programs.
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