FT2232H：全能USB转换芯片，集成高速接口

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DT2232 数据手册是Future Technology Devices International Limited (FTDI)推出的一款高级多功能USB接口转换器，名为FT2232H。该芯片是FTDI的第五代产品，专为USB 2.0 High Speed（480 Mb/s）通信设计，集成了多种功能，旨在简化工业标准串行或并行接口的硬件设计。首先，FT2232H的特点在于其单芯片设计，可配置为两个独立的串行/并行端口，提供了极大的灵活性，适应不同应用场景的需求。这使得开发人员无需专门编写针对USB协议的固件程序，大大减少了编程复杂性。该芯片支持两种USB传输速率：USB 2.0 High Speed（480 Mbits/秒）和Full Speed（12 Mbits/秒），确保了与不同设备的兼容性。这对于需要快速数据传输的项目尤其有用，无论是高速数据交换还是传统串口通信，都能应对自如。 FT2232H还配备了双多协议同步串行引擎（MPSSE），有助于实现简单的同步串行协议转换，如USB到JTAG、I2C或SPI接口。这意味着它可以作为一个通用的接口控制器，用于处理多种不同的通信标准，提高了系统的集成度和效率。此外，它具有两个独立的UART（通用异步收发器）、FIFO（先进先出队列）或MPSSE端口，每个端口可以独立配置，满足不同任务的实时性和数据缓冲需求。内置的独立波特率发生器允许灵活调整各个串口的通信速度，包括最高可达12 Mbaud的RS232/RS422/RS485 UART数据传输。值得注意的是，RS232的数据传输速率受到外部电路的影响，但FT2232H本身提供了足够的功能来优化这一过程。FT2232H作为一款强大的多功能USB转换器，为工业界提供了高效、灵活且易于使用的解决方案，广泛应用于嵌入式系统、仪器仪表、工业自动化和消费电子等领域。

FT2232H Dual High Speed USB to Multipurpose UART/FIFO IC

Datasheet

Version 2.5

Document No.: FT_000061 Clearance No.: FTDI#77

3.1.4.3 FT2232H pins used in an FT245 Style Asynchronous FIFO Interface

The FT2232H channel A or channel B can be configured as a FT245 asynchronous FIFO interface. When

configured in this mode, the pins used and the descriptions of the signals are shown in Table 3.7. To

enter this mode the external EEPROM must be set to make port A or B or both 245 mode. In this mode,

data is written or read on the falling edge of the RD# or WR# signals.

Channel A

Pin No.

Channel B

Pin No.

Name

Type

FT245 Configuration Description

24,23,22,21,

19,18,17,16

46,45,44,43,

41,40,39,38

Channel A =

ADBUS[7:0]

Channel B =

BDBUS[7:0]

I/O

D7 to D0 bidirectional FIFO data. This bus is normally input

unless RD# is low.

RXF#

OUTPUT

When high, do not read data from the FIFO. When low,

there is data available in the FIFO which can be read by

driving RD# low. When RD# goes high again RXF# will

always go high and only become low again if there is

another byte to read. During reset this signal pin is tri-

state, but pulled up to VCCIO via an internal 200kΩ

resistor.

TXE#

OUTPUT

When high, do not write data into the FIFO. When low, data

can be written into the FIFO by strobing WR# high, then

low. During reset this signal pin is tri-state, but pulled up to

VCCIO via an internal 200kΩ resistor.

RD#

INPUT

Enables the current FIFO data byte to be driven onto

D0...D7 when RD# goes low. Fetches the next FIFO data

byte (if available) from the receive FIFO buffer when RD#

goes high.

WR#

INPUT

Writes the data byte on the D0...D7 pins into the transmit

FIFO buffer when WR# goes from high to low.

SIWU

INPUT

The Send Immediate / WakeUp signal combines two

functions on a single pin. If USB is in suspend mode

(PWREN# = 1) and remote wakeup is enabled in the

EEPROM, strobing this pin low will cause the device to

request a resume on the USB Bus. Normally, this can be

used to wake up the Host PC.

During normal operation (PWREN# = 0), if this pin is

strobed low any data in the device TX buffer will be sent out

over USB on the next Bulk-IN request from the drivers

regardless of the pending packet size. This can be used to

optimize USB transfer speed for some applications. Tie this

pin to VCCIO if not used. (Also see note 1, 2, 3 in section

4.12)

Table 3.7 Channel A and Channel B FT245 Style Asynchronous FIFO Configured Pin

Descriptions

FT2232H Dual High Speed USB to Multipurpose UART/FIFO IC

Datasheet

Version 2.5

Document No.: FT_000061 Clearance No.: FTDI#77

3.1.4.4 FT2232H pins used in a Synchronous or Asynchronous Bit-Bang Interface

The FT2232H channel A or channel B can be configured as a synchronous or asynchronous bit-bang

interface. Bit-bang mode is a special FTDI FT2232H device mode that changes the 8 IO lines on either (or

both) channels into an 8 bit bi-directional data bus. There are two types of bit-bang modes: synchronous

and asynchronous.

When configured in any bit-bang mode, the pins used and the descriptions of the signals are shown in

Table 3.8

Channel A

Pin No.

Channel B

Pin No.

Name

Type

Configuration Description

24,23,22,21

19,18,17,16

46,45,44,43,

41,40,39,38

Channel A =

ADBUS[7:0]

Channel B =

BDBUS[7:0]

I/O

D7 to D0 bidirectional Bit-Bang parallel I/O

data pins

WRSTB#

OUTPUT

Write strobe, active low output indicates

when new data has been written to the I/O

pins from the Host PC (via the USB

interface).

RDSTB#

OUTPUT

Read strobe, this output rising edge

indicates when data has been read from the

parallel I/O pins and sent to the Host PC

(via the USB interface).

SIWU

INPUT

The Send Immediate / WakeUp signal

combines two functions on a single pin. If

USB is in suspend mode (PWREN# = 1) and

remote wakeup is enabled in the EEPROM,

strobing this pin low will cause the device to

request a resume on the USB Bus.

Normally, this can be used to wake up the

Host PC.

During normal operation (PWREN# = 0), if

this pin is strobed low any data in the device

TX buffer will be sent out over USB on the

next Bulk-IN request from the drivers

regardless of the pending packet size. This

can be used to optimize USB transfer speed

for some applications. Tie this pin to VCCIO

if not used. (Also see note 1, 2, 3 in section

4.12)

Table 3.8 Channel A and Channel B Synchronous or Asynchronous Bit-Bang Configured Pin

Descriptions

For a functional description of this mode, please refer to section 4.10 Synchronous and Asynchronous Bit-

Bang Interface Mode Description.

FT2232H Dual High Speed USB to Multipurpose UART/FIFO IC

Datasheet

Version 2.5

Document No.: FT_000061 Clearance No.: FTDI#77

3.1.4.5 FT2232H pins used in an MPSSE

The FT2232H channel A and channel B, each have a Multi-Protocol Synchronous Serial Engine (MPSSE).

Each MPSSE can be independently configured to a number of industry standard serial interface protocols

such as JTAG, I2C or SPI, or it can be used to implement a proprietary bus protocol. For example, it is

possible to use one of the FT2232H’s channels to connect to an SRAM configurable FPGA such as supplied

by Altera or Xilinx. The FPGA device would normally be un-configured (i.e. have no defined function) at

power-up. Application software on the PC could use the MPSSE to download configuration data to the

FPGA over USB. This data would define the hardware function on power up. The other FT2232H channel

would be available for another function. Alternatively each MPSSE can be used to control a number of

GPIO pins. When configured in this mode, the pins used and the descriptions of the signals are shown

Table 3.9

Channel A

Pin No.

Channel B

Pin No.

Name

Type

MPSSE Configuration Description

TCK/SK

OUTPUT

Clock Signal Output. For example:

JTAG – TCK, Test interface clock

SPI – SK, Serial Clock

TDI/DO

OUTPUT

Serial Data Output. For example:

JTAG – TDI, Test Data Input

SPI – DO

TDO/DI

INPUT

Serial Data Input. For example:

JTAG – TDO, Test Data output

SPI – DI, Serial Data Input

TMS/CS

OUTPUT

Output Signal Select. For example:

JTAG – TMS, Test Mode Select

SPI – CS, Serial Chip Select

GPIOL0

I/O

General Purpose input/output

GPIOL1

I/O

General Purpose input/output

GPIOL2

I/O

General Purpose input/output

GPIOL3

I/O

General Purpose input/output

GPIOH0

I/O

General Purpose input/output

GPIOH1

I/O

General Purpose input/output

GPIOH2

I/O

General Purpose input/output

GPIOH3

I/O

General Purpose input/output

GPIOH4

I/O

General Purpose input/output

GPIOH5

I/O

General Purpose input/output

GPIOH6

I/O

General Purpose input/output

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