STM32G041K8 Cortex-M0+ 单片机技术规格

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"STM32G041K8是STMicroelectronics公司生产的一款基于Arm Cortex-M0+内核的32位微控制器。这款微控制器适用于全速生产，具有多种功能和特性，如高达64KB的闪存、8KB带硬件奇偶校验检查的SRAM、2个USART、定时器、ADC、通信接口、AES加密和随机数生成器，工作电压范围在1.7V到3.6V之间，并具备各种低功耗模式。" STM32G041K8的关键特性包括： 1. **处理器核心**：该微控制器搭载了Arm Cortex-M0+处理器，运行频率最高可达64MHz，提供了高效能的处理能力，适合于嵌入式应用。 2. **温度范围**：能够在-40°C至85°C的宽温范围内正常工作，部分型号甚至支持125°C的高温操作，使其适应各种环境条件。 3. **内存配置**：提供最大64KB的闪存用于存储程序代码和数据，以及8KB的SRAM作为工作内存，且SRAM带有硬件奇偶校验功能，增强了数据完整性。 4. **错误检测与电源管理**：集成CRC计算单元，确保数据传输的准确性；工作电压范围在1.7V到3.6V，具备POR（上电复位）、PDR（掉电复位）、BOR（可编程 brownout 复位）和PVD（可编程电压检测器），以及多种低功耗模式，如睡眠、停止、待机和关机，同时支持VBAT供电，用于RTC（实时时钟）和备份寄存器。 5. **时钟系统**：包含4到48MHz的晶体振荡器，32kHz的晶体振荡器可进行校准，16MHz的内部RC振荡器（精度±1%）以及32kHz的内部RC振荡器（精度±5%），为系统提供多样化的时钟源选择。 6. **输入/输出(I/O)**：最多44个快速I/O，所有I/O都可映射到外部中断向量，且部分I/O具有5V耐受能力，增强了系统的兼容性和可靠性。 7. **DMA控制器**：5通道DMA控制器，允许灵活的数据传输映射，减轻CPU负担。 8. **模拟功能**：集成了12位ADC，转换速度可达0.4μs，最多支持16个外部通道，支持硬件过采样，最高可达到16位分辨率。 9. **其他外设**：还包括AES加密单元和随机数生成器，增强了数据安全性和系统的随机性需求。 STM32G041K8是面向多种应用设计的，如物联网设备、智能家居、工业控制、消费电子等，其丰富的功能和低功耗特性使其成为嵌入式系统开发的理想选择。开发者可以利用这些特性实现高效、可靠的嵌入式系统设计。

Functional overview STM32G041x6/x8

16/118 DS12993 Rev 1

externally through VBAT pin. When this pin is not available on the package, VBAT

bonding pad is internally bonded to the VDD/VDDA pin.

• V

REF+

is the input reference voltage for the ADC, or the output of the internal voltage

reference buffer (when enabled). When V

DDA

< 2 V, V

REF+

must be equal to V

DDA

When V

DDA

≥ 2 V, V

REF+

must be between 2 V and V

DDA

. It can be grounded when the

ADC is not active.

The internal voltage reference buffer supports two output voltages, which is configured

with VRS bit of the VREFBUF_CSR register:

–V

REF+

around 2.048 V (requiring V

DDA

equal to or higher than 2.4 V)

–V

REF+

around 2.5 V (requiring V

DDA

equal to or higher than 2.8 V)

REF+

is delivered through VREF+ pin. On packages without VREF+ pin, V

REF+

internally connected with V

, and the internal voltage reference buffer must be kept

disabled (refer to datasheets for package pinout description).

• V

CORE

An embedded linear voltage regulator is used to supply the V

CORE

internal digital

power. V

CORE

is the power supply for digital peripherals, SRAM and Flash memory.

The Flash memory is also supplied with V

Figure 2. Power supply overview

3.7.2 Power supply supervisor

The device has an integrated power-on/power-down (POR/PDR) reset active in all power

modes except Shutdown and ensuring proper operation upon power-on and power-down. It

maintains the device in reset when the supply voltage is below V

POR/PDR

threshold, without

the need for an external reset circuit. Brownout reset (BOR) function allows extra flexibility. It

MSv47940V1

DDA

domain

RTC domain

A/D converter

Standby circuitry

(Wakeup logic,

IWDG)

Voltage regulator

Core

SRAM

Digital

peripherals

Low-voltage

detector

LSE crystal 32.768 KHz osc

BKP registers

RCC BDCR register

RTC

Voltage reference buffer

I/O ring

CORE

domain

Temp. sensor

Reset block

PLL, HSI

Flash memory

DDIO1

VREF+

domain

CORE

VSS

VDD

VBAT

DDA

REF+

SSA

DS12993 Rev 1 17/118

STM32G041x6/x8 Functional overview

can be enabled and configured through option bytes, by selecting one of four thresholds for

rising V

and other four for falling V

The device also features an embedded programmable voltage detector (PVD) that monitors

the V

power supply and compares it to V

PVD

threshold. It allows generating an interrupt

when V

level crosses the V

PVD

threshold, selectively while falling, while rising, or while

falling and rising. The interrupt service routine can then generate a warning message and/or

put the MCU into a safe state. The PVD is enabled by software.

3.7.3 Voltage regulator

Two embedded linear voltage regulators, main regulator (MR) and low-power regulator

(LPR), supply most of digital circuitry in the device.

The MR is used in Run and Sleep modes. The LPR is used in Low-power run, Low-power

sleep and Stop modes.

In Standby and Shutdown modes, both regulators are powered down and their outputs set in

high-impedance state, such as to bring their current consumption close to zero. However,

SRAM data retention is possible in Standby mode, in which case the LPR remains active

and it only supplies the SRAM.

3.7.4 Low-power modes

By default, the microcontroller is in Run mode after system or power reset. It is up to the

user to select one of the low-power modes described below:

• Sleep mode

In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can

wake up the CPU when an interrupt/event occurs.

• Low-power run mode

This mode is achieved with V

CORE

supplied by the low-power regulator to minimize the

regulator's operating current. The code can be executed from SRAM or from Flash,

and the CPU frequency is limited to 2 MHz. The peripherals with independent clock can

be clocked by HSI16.

• Low-power sleep mode

This mode is entered from the low-power run mode. Only the CPU clock is stopped.

When wakeup is triggered by an event or an interrupt, the system reverts to the Low-

power run mode.

• Stop 0 and Stop 1 modes

In Stop 0 and Stop 1 modes, the device achieves the lowest power consumption while

retaining the SRAM and register contents. All clocks in the V

CORE

domain are stopped.

The PLL, as well as the HSI16 RC oscillator and the HSE crystal oscillator are

disabled. The LSE or LSI keep running. The RTC can remain active (Stop mode with

RTC, Stop mode without RTC).

Some peripherals with wakeup capability can enable the HSI16 RC during Stop mode,

so as to get clock for processing the wakeup event. The main regulator remains active

in Stop 0 mode while it is turned off in Stop 1 mode.

• Standby mode

The Standby mode is used to achieve the lowest power consumption, with POR/PDR

always active in this mode. The main regulator is switched off to power down V

CORE

domain. The low-power regulator is either switched off or kept active. In the latter case,

Functional overview STM32G041x6/x8

18/118 DS12993 Rev 1

it only supplies SRAM to ensure data retention. The PLL, as well as the HSI16 RC

oscillator and the HSE crystal oscillator are also powered down. The RTC can remain

active (Standby mode with RTC, Standby mode without RTC).

For each I/O, the software can determine whether a pull-up, a pull-down or no resistor

shall be applied to that I/O during Standby mode.

Upon entering Standby mode, register contents are lost except for registers in the RTC

domain and standby circuitry. The SRAM contents can be retained through register

setting.

The device exits Standby mode upon external reset event (NRST pin), IWDG reset

event, wakeup event (WKUP pin, configurable rising or falling edge) or RTC event

(alarm, periodic wakeup, timestamp, tamper), or when a failure is detected on LSE

(CSS on LSE).

• Shutdown mode

The Shutdown mode allows to achieve the lowest power consumption. The internal

regulator is switched off to power down the V

CORE

domain. The PLL, as well as the

HSI16 and LSI RC-oscillators and HSE crystal oscillator are also powered down. The

RTC can remain active (Shutdown mode with RTC, Shutdown mode without RTC).

The BOR is not available in Shutdown mode. No power voltage monitoring is possible

in this mode. Therefore, switching to RTC domain is not supported.

SRAM and register contents are lost except for registers in the RTC domain.

The device exits Shutdown mode upon external reset event (NRST pin), IWDG reset

event, wakeup event (WKUP pin, configurable rising or falling edge) or RTC event

(alarm, periodic wakeup, timestamp, tamper).

3.7.5 Reset mode

During and upon exiting reset, the schmitt triggers of I/Os are disabled so as to reduce

power consumption. In addition, when the reset source is internal, the built-in pull-up

resistor on NRST pin is deactivated.

3.7.6 VBAT operation

The V

BAT

power domain, consuming very little energy, includes RTC, and LSE oscillator and

backup registers.

In VBAT mode, the RTC domain is supplied from VBAT pin. The power source can be, for

example, an external battery or an external supercapacitor. Two anti-tamper detection pins

are available.

The RTC domain can also be supplied from VDD/VDDA pin.

By means of a built-in switch, an internal voltage supervisor allows automatic switching of

RTC domain powering between V

and voltage from VBAT pin to ensure that the supply

voltage of the RTC domain (V

BAT

) remains within valid operating conditions. If both voltages

are valid, the RTC domain is supplied from VDD/VDDA pin.

An internal circuit for charging the battery on VBAT pin can be activated if the V

voltage is

within a valid range.

Note: External interrupts and RTC alarm/events cannot cause the microcontroller to exit the VBAT

mode, as in that mode the V

is not within a valid range.

Functional overview STM32G041x6/x8

20/118 DS12993 Rev 1

3.9 Clocks and startup

The clock controller distributes the clocks coming from different oscillators to the core and

the peripherals. It also manages clock gating for low-power modes and ensures clock

robustness. It features:

• Clock prescaler: to get the best trade-off between speed and current consumption,

the clock frequency to the CPU and peripherals can be adjusted by a programmable

prescaler

• Safe clock switching: clock sources can be changed safely on the fly in run mode

through a configuration register.

• Clock management: to reduce power consumption, the clock controller can stop the

clock to the core, individual peripherals or memory.

• System clock source: three different sources can deliver SYSCLK system clock:

– 4-48 MHz high-speed oscillator with external crystal or ceramic resonator (HSE). It

can supply clock to system PLL. The HSE can also be configured in bypass mode

for an external clock.

– 16 MHz high-speed internal RC oscillator (HSI16), trimmable by software. It can

supply clock to system PLL.

– System PLL with maximum output frequency of 64 MHz. It can be fed with HSE or

HSI16 clocks.

• Auxiliary clock source: two ultra-low-power clock sources for the real-time clock

(RTC):

– 32.768 kHz low-speed oscillator with external crystal (LSE), supporting four drive

capability modes. The LSE can also be configured in bypass mode for using an

external clock.

– 32 kHz low-speed internal RC oscillator (LSI) with ±5% accuracy, also used to

clock an independent watchdog.

• Peripheral clock sources: several peripherals (I2S, USARTs, I2Cs, LPTIMs, ADC)

have their own clock independent of the system clock.

• Clock security system (CSS): in the event of HSE clock failure, the system clock is

automatically switched to HSI16 and, if enabled, a software interrupt is generated. LSE

clock failure can also be detected and generate an interrupt. The CCS feature can be

enabled by software.

• Clock output:

– MCO (microcontroller clock output) provides one of the internal clocks for

external use by the application

– LSCO (low speed clock output) provides LSI or LSE in all low-power modes

(except in VBAT operation).

Several prescalers allow the application to configure AHB and APB domain clock

frequencies, 64 MHz at maximum.

3.10 General-purpose inputs/outputs (GPIOs)

Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as

input (with or without pull-up or pull-down) or as peripheral alternate function (AF). Most of

the GPIO pins are shared with special digital or analog functions.

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