Allwinner A10用户手册 - v1.20 (2012-04-09)

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"A10 User Manual - v1.20 (2012-04-09, DECRYPTED)" 是一份针对Allwinner Technology公司的A10处理器的用户手册，版本号为V1.20，日期为2012年4月9日。该手册详细介绍了A10处理器的特性和使用方法，适用于Arduino平台。在手册中，我们可以看到修订历史，表明从V1.00到V1.20的不同版本中对音频编解码器和USB部分进行了更新和修正。这表示手册内容随着技术的发展不断得到完善和优化。技术项目部分列出了A10处理器的关键组件和特性： 1. ARM Cortex™-A8: 这是ARM Holdings设计的一种处理器核心，它实现了ARMv7指令集架构，是A10处理器的基础，提供高性能的计算能力。 2. Mali-400: 这是一款由ARM Holdings设计的2D/3D图形处理器单元，用于处理图形渲染和游戏等任务，对于多媒体应用和用户界面的流畅性至关重要。 3. SDRAM（Synchronous Dynamic Random Access Memory）: A10处理器采用同步动态随机存取内存，这种内存类型与系统总线同步，提供了高速的数据存取速度，是处理器运行时的重要缓存。 4. PWM（Pulse Width Modulation）: 这是一种模拟输出技术，通过调整脉冲宽度来改变信号的平均值，常用于控制电机速度、LED亮度调节以及电源管理等多种应用。 A10处理器是基于ARM Cortex™-A8内核的，集成了Mali-400 GPU以支持图形处理，并配备SDRAM进行高效数据交换。手册还涉及了PWM技术的应用，表明A10在硬件控制和交互方面具有灵活性。此外，随着版本更新，处理器的音频处理和USB功能得到了改进，提升了整体性能和用户体验。对于Arduino用户来说，这份手册是理解和使用A10处理器不可或缺的参考资料。

For WITS Only

Allwinner Technology CO., Ltd. A10

A10 User Manual V1.20

2012-04-09

30.3.18. PB Pull Register 1 .................................................................................................................. 298

30.3.19. PC Configure Register 0 ........................................................................................................ 298

30.3.20. PC Configure Register 1 ........................................................................................................ 299

30.3.21. PC Configure Register 2 ........................................................................................................ 301

30.3.22. PC Configure Register 3 ........................................................................................................ 302

30.3.23. PC Data Register .................................................................................................................... 302

30.3.24. PC Multi-Driving Register 0 .................................................................................................. 303

30.3.25. PC Multi-Driving Register 1 .................................................................................................. 303

30.3.26. PC Pull Register 0 .................................................................................................................. 303

30.3.27. PC Pull Register 1 .................................................................................................................. 303

30.3.28. PD Configure Register 0 ........................................................................................................ 304

30.3.29. PD Configure Register 1 ........................................................................................................ 305

30.3.30. PD Configure Register 2 ........................................................................................................ 306

30.3.31. PD Configure Register 3 ........................................................................................................ 307

30.3.32. PD Data Register .................................................................................................................... 308

30.3.33. PD Multi-Driving Register 0 .................................................................................................. 309

30.3.34. PD Multi-Driving Register 1 .................................................................................................. 309

30.3.35. PD Pull Register 0 .................................................................................................................. 309

30.3.36. PD Pull Register 1 .................................................................................................................. 309

30.3.37. PE Configure Register 0 ......................................................................................................... 310

30.3.38. PE Configure Register 1 ......................................................................................................... 311

30.3.39. PE Configure Register 2 ......................................................................................................... 312

30.3.40. PE Configure Register 3 ......................................................................................................... 312

30.3.41. PE Data Register .................................................................................................................... 312

30.3.42. PE Multi-Driving Register 0 .................................................................................................. 312

30.3.43. PE Multi-Driving Register 1 .................................................................................................. 313

30.3.44. PE Pull Register 0 .................................................................................................................. 313

30.3.45. PE Pull Register 1 .................................................................................................................. 313

30.3.46. PF Configure Register 0 ......................................................................................................... 313

30.3.47. PF Configure Register 1 ......................................................................................................... 314

30.3.48. PF Configure Register 2 ......................................................................................................... 314

30.3.49. PF Configure Register 3 ......................................................................................................... 315

30.3.50. PF Data Register .................................................................................................................... 315

30.3.51. PF Multi-Driving Register 0 .................................................................................................. 315

30.3.52. PF Multi-Driving Register 1 .................................................................................................. 315

30.3.53. PF Pull Register 0................................................................................................................... 316

30.3.54. PF Pull Register 1................................................................................................................... 316

30.3.55. PG Configure Register 0 ........................................................................................................ 316

30.3.56. PG Configure Register 1 ........................................................................................................ 317

30.3.57. PG Configure Register 2 ........................................................................................................ 318

30.3.58. PG Configure Register 3 ........................................................................................................ 318

30.3.59. PG Data Register .................................................................................................................... 318

30.3.60. PG Multi-Driving Register 0 .................................................................................................. 319

30.3.61. PG Multi-Driving Register 1 .................................................................................................. 319

For WITS Only

Allwinner Technology CO., Ltd. A10

A10 User Manual V1.20

2012-04-09

30.3.62. PG Pull Register 0 .................................................................................................................. 319

30.3.63. PG Pull Register 1 .................................................................................................................. 319

30.3.64. PH Configure Register 0 ........................................................................................................ 320

30.3.65. PH Configure Register 1 ........................................................................................................ 321

30.3.66. PH Configure Register 2 ........................................................................................................ 322

30.3.67. PH Configure Register 3 ........................................................................................................ 323

30.3.68. PH Data Register .................................................................................................................... 324

30.3.69. PH Multi-Driving Register 0 .................................................................................................. 325

30.3.70. PH Multi-Driving Register 1 .................................................................................................. 325

30.3.71. PH Pull Register 0 .................................................................................................................. 325

30.3.72. PH Pull Register 1 .................................................................................................................. 325

30.3.73. PI Configure Register 0 .......................................................................................................... 326

30.3.74. PI Configure Register 1 .......................................................................................................... 327

30.3.75. PI Configure Register 2 .......................................................................................................... 328

30.3.76. PI Configure Register 3 .......................................................................................................... 329

30.3.77. PI Data Register ..................................................................................................................... 329

30.3.78. PI Multi-Driving Register 0 ................................................................................................... 330

30.3.79. PI Multi-Driving Register 1 ................................................................................................... 330

30.3.80. PI Pull Register 0 ................................................................................................................... 330

30.3.81. PI Pull Register 1 ................................................................................................................... 330

30.3.82. PIO Interrupt Configure Register 0 ........................................................................................ 331

30.3.83. PIO Interrupt Configure Register 1 ........................................................................................ 331

30.3.84. PIO Interrupt Configure Register 2 ........................................................................................ 331

30.3.85. PIO Interrupt Configure Register 3 ........................................................................................ 332

30.3.86. PIO Interrupt Control Register ............................................................................................... 332

30.3.87. PIO Interrupt Status Register ................................................................................................. 332

30.3.88. PIO Interrupt Debounce Register ........................................................................................... 333

31. CSI0 with ISP FE ................................................................................................................................. 334

31.1. Overview ........................................................................................................................................ 334

31.2. Feature ............................................................................................................................................ 334

31.2.1. CSI ......................................................................................................................................... 334

31.2.2. ISP FE .................................................................................................................................... 334

31.3. Block diagram ................................................................................................................................ 335

31.3.1. CSI data ports ......................................................................................................................... 335

31.4. Timing ............................................................................................................................................ 335

31.4.1. CSI timing .............................................................................................................................. 335

31.4.2. 16bit YUV422 Timing ........................................................................................................... 336

31.4.3. CCIR656 2 channel Timing ................................................................................................... 336

31.4.4. CCIR656 4 channel Timing ................................................................................................... 337

31.4.5. CCIR656 Header Code .......................................................................................................... 337

31.5. CSI0 Register List .......................................................................................................................... 338

For WITS Only

Allwinner Technology CO., Ltd. A10

A10 User Manual V1.20

2012-04-09

31.6. CSI0 Register Description.............................................................................................................. 343

31.6.1. CSI Enable Register ............................................................................................................... 343

31.6.2. CSI configuration register ...................................................................................................... 343

31.6.3. CSI capture control register ................................................................................................... 345

31.6.4. CSI horizontal scale register .................................................................................................. 346

31.6.5. CSI Channel_0 FIFO 0 output buffer-A address register ....................................................... 346

31.6.6. CSI Channel_0 FIFO 0 output buffer-B address register ....................................................... 346

31.6.7. CSI Channel_0 FIFO 1 output buffer-A address register ....................................................... 347

31.6.8. CSI Channel_0 FIFO 1 output buffer-B address register ....................................................... 347

31.6.9. CSI Channel_0 FIFO 2 output buffer-A address register ....................................................... 347

31.6.10. CSI Channel_0 FIFO 2 output buffer-B address register ....................................................... 347

31.6.11. CSI Channel_0 output buffer control register ........................................................................ 347

31.6.12. CSI Channel_0 status register ................................................................................................ 348

31.6.13. CSI Channel_0 interrupt enable register ................................................................................ 349

31.6.14. CSI Channel_0 interrupt status register ................................................................................. 350

31.6.15. CSI Channel_0 horizontal size register .................................................................................. 350

31.6.16. CSI Channel_0 vertical size register ...................................................................................... 350

31.6.17. CSI Channel_0 buffer length register ..................................................................................... 351

31.6.18. CSI Channel_1 FIFO 0 output buffer-A address register ....................................................... 351

31.6.19. CSI Channel_1 FIFO 0 output buffer-B address register ....................................................... 351

31.6.20. CSI Channel_1 FIFO 1 output buffer-A address register ....................................................... 351

31.6.21. CSI Channel_1 FIFO 1 output buffer-B address register ....................................................... 352

31.6.22. CSI Channel_1 FIFO 2 output buffer-A address register ....................................................... 352

31.6.23. CSI Channel_1 FIFO 2 output buffer-B address register ....................................................... 352

31.6.24. CSI Channel_1 output buffer control register ........................................................................ 352

31.6.25. CSI Channel_1 status register ................................................................................................ 353

31.6.26. CSI Channel_1 interrupt enable register ................................................................................ 353

31.6.27. CSI Channel_1 interrupt status register ................................................................................. 354

31.6.28. CSI Channel_1 horizontal size register .................................................................................. 355

31.6.29. CSI Channel_1 vertical size register ...................................................................................... 355

31.6.30. CSI Channel_1 buffer length register ..................................................................................... 356

31.6.31. CSI Channel_2 FIFO 0 output buffer-A address register ....................................................... 356

31.6.32. CSI Channel_2 FIFO 0 output buffer-B address register ....................................................... 356

31.6.33. CSI Channel_2 FIFO 1 output buffer-A address register ....................................................... 356

31.6.34. CSI Channel_2 FIFO 1 output buffer-B address register ....................................................... 356

31.6.35. CSI Channel_2 FIFO 2 output buffer-A address register ....................................................... 357

31.6.36. CSI Channel_2 FIFO 2 output buffer-B address register ....................................................... 357

31.6.37. CSI Channel_2 output buffer control register ........................................................................ 357

31.6.38. CSI Channel_2 status register ................................................................................................ 358

31.6.39. CSI Channel_2 interrupt enable register ................................................................................ 358

31.6.40. CSI Channel_2 interrupt status register ................................................................................. 359

31.6.41. CSI Channel_2 horizontal size register .................................................................................. 360

31.6.42. CSI Channel_2 vertical size register ...................................................................................... 360

31.6.43. CSI Channel_2 buffer length register ..................................................................................... 360

For WITS Only

Allwinner Technology CO., Ltd. A10

A10 User Manual V1.20

2012-04-09

31.6.44. CSI Channel_3 FIFO 0 output buffer-A address register ....................................................... 361

31.6.45. CSI Channel_3 FIFO 0 output buffer-B address register ....................................................... 361

31.6.46. CSI Channel_3 FIFO 1 output buffer-A address register ....................................................... 361

31.6.47. CSI Channel_3 FIFO 1 output buffer-B address register ....................................................... 361

31.6.48. CSI Channel_3 FIFO 2 output buffer-A address register ....................................................... 361

31.6.49. CSI Channel_3 FIFO 2 output buffer-B address register ....................................................... 362

31.6.50. CSI Channel_3 output buffer control register ........................................................................ 362

31.6.51. CSI Channel_3 status register ................................................................................................ 362

31.6.52. CSI Channel_3 interrupt enable register ................................................................................ 363

31.6.53. CSI Channel_3 interrupt status register ................................................................................. 364

31.6.54. CSI Channel_3 horizontal size register .................................................................................. 364

31.6.55. CSI Channel_3 vertical size register ...................................................................................... 365

31.6.56. CSI Channel_3 buffer length register ..................................................................................... 365

31.6.57. ISP Enable register ................................................................................................................. 365

31.6.58. ISP Mode register ................................................................................................................... 366

31.6.59. ISP OBC Image Black size register........................................................................................ 367

31.6.60. ISP OBC Image Valid size register ........................................................................................ 367

31.6.61. ISP OBC Image Start register................................................................................................. 367

31.6.62. ISP OBC configuration register ............................................................................................. 368

31.6.63. ISP Horizontal OBC window start register ............................................................................ 368

31.6.64. ISP Vertical OBC window start register ................................................................................. 369

31.6.65. ISP Vertical OBC parameter register ...................................................................................... 369

31.6.66. ISP OBC fixed value register ................................................................................................. 369

31.6.67. ISP OBC offset register .......................................................................................................... 370

31.6.68. ISP OBC clamp value register ................................................................................................ 370

31.6.69. ISP LSC configuration register .............................................................................................. 370

31.6.70. ISP LSC gain factor address register ...................................................................................... 371

31.6.71. ISP LSC gain factor address length register ........................................................................... 371

31.6.72. ISP Offset register .................................................................................................................. 371

31.6.73. ISP Gain Factor register ......................................................................................................... 371

31.6.74. ISP Dark Frame Enable register ............................................................................................. 372

31.6.75. ISP Dark Frame buffer address register ................................................................................. 372

31.6.76. ISP Dark Frame buffer address length register ...................................................................... 372

31.6.77. ISP luma DC subtraction value register ................................................................................. 373

31.6.78. ISP H3A Median filter threshold register ............................................................................... 373

31.6.79. ISP AF window number register ............................................................................................ 373

31.6.80. ISP AF window size register .................................................................................................. 374

31.6.81. ISP AF window start register.................................................................................................. 374

31.6.82. ISP AF configuration register ................................................................................................. 374

31.6.83. ISP AF filter parameter 0 register ........................................................................................... 375

31.6.84. ISP AF filter parameter 1 register ........................................................................................... 375

31.6.85. ISP AF filter parameter 2 register ........................................................................................... 375

31.6.86. ISP AWBE window number register ...................................................................................... 376

31.6.87. ISP AWBE window size register ............................................................................................ 376

For WITS Only

Allwinner Technology CO., Ltd. A10

A10 User Manual V1.20

2012-04-09

31.6.88. ISP AWBE window start register ........................................................................................... 376

31.6.89. ISP AWBE configuration register .......................................................................................... 377

31.6.90. ISP Histogram region 0 window size register ........................................................................ 377

31.6.91. ISP Histogram region 0 window start register ....................................................................... 377

31.6.92. ISP Histogram region 1 window size register ........................................................................ 378

31.6.93. ISP Histogram region 1 window start register ....................................................................... 378

31.6.94. ISP Histogram region 2 window size register ........................................................................ 378

31.6.95. ISP Histogram region 2 window start register ....................................................................... 379

31.6.96. ISP Histogram region 3 window size register ........................................................................ 379

31.6.97. ISP Histogram region 3 window start register ....................................................................... 379

31.6.98. ISP 3A Statistics output address register ................................................................................ 380

31.6.99. ISP LUT Defect Correction configuration register ................................................................ 380

31.6.100. ISP LUT Defect Correction address register .......................................................................... 380

31.6.101. ISP FE Y/Raw Output address length register ....................................................................... 381

31.6.102. SP FE Y/Raw Output address register .................................................................................... 381

31.6.103. ISP interrupt enable register ................................................................................................... 381

31.6.104. ISP interrupt status register .................................................................................................... 382

31.6.105. ISP FE CbCr Output address length register .......................................................................... 382

31.6.106. ISP FE CbCr Output address register ..................................................................................... 383

32. CSI1 ....................................................................................................................................................... 384

32.1. Overview ........................................................................................................................................ 384

32.2. Block diagram ................................................................................................................................ 384

32.3. CSI data ports ................................................................................................................................. 385

32.4. Timing ............................................................................................................................................ 385

32.4.1. CSI timing .............................................................................................................................. 385

32.5. CSI1 Registers List ........................................................................................................................ 385

32.6. CSI1 Register Description.............................................................................................................. 386

32.6.1. CSI Enable Register ............................................................................................................... 386

32.6.2. CSI configuration register ...................................................................................................... 387

32.6.3. CSI capture control register ................................................................................................... 389

32.6.4. CSI horizontal scale register .................................................................................................. 389

32.6.5. CSI Channel_0 FIFO 0 output buffer-A address register ....................................................... 390

32.6.6. CSI Channel_0 FIFO 0 output buffer-B address register ....................................................... 390

32.6.7. CSI Channel_0 FIFO 1 output buffer-A address register ....................................................... 390

32.6.8. CSI Channel_0 FIFO 1 output buffer-B address register ....................................................... 391

32.6.9. CSI Channel_0 FIFO 2 output buffer-A address register ....................................................... 391

32.6.10. CSI Channel_0 FIFO 2 output buffer-B address register ....................................................... 391

32.6.11. CSI Channel_0 output buffer control register ........................................................................ 391

32.6.12. CSI Channel_0 status register ................................................................................................ 392

32.6.13. CSI Channel_0 interrupt enable register ................................................................................ 393

32.6.14. CSI Channel_0 interrupt status register ................................................................................. 394

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