GCC移植入门指南，从零开始学习移植技术。

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"Porting GCC for Dunces" is a comprehensive guide written by Hans-Peter Nilsson on the process of porting the GNU Compiler Collection (GCC) for individuals with limited experience in compiler development. The document begins with a legal notice and proceeds to provide an introduction that outlines the background of compilers and the purpose of the work at hand. Nilsson emphasizes the significance of compilers in software development and highlights the importance of porting GCC for various platforms. The document aims to simplify the complex process of porting GCC for beginners, hence the title "Porting GCC for Dunces". The author provides a detailed explanation of the steps involved in porting GCC and the challenges that may arise during the process. The result of the porting work is discussed, showcasing the benefits of having GCC available on different platforms and the impact it can have on software development. Nilsson also outlines the restrictions in the document, setting clear guidelines for readers on what to expect and what not to expect from the information provided. Overall, "Porting GCC for Dunces" serves as a valuable resource for individuals looking to expand their knowledge in compiler development and contribute to the enhancement of software tools. The document is a testament to the author's expertise and dedication to making complex technical concepts more accessible to a wider audience.

16 CHAPTER 2. INTRODUCTION

18 CHAPTER 3. THE TARGET SYSTEM

Addressable register parts

ccr

srp

Some special registers

XXixnzvc

Classic condition codes

Subroutine return pointer

2 .. n

Execution of simple instructions (prefix instructions are extra)

State 1: Fetch and

execute instruction

State 2 .. n: Get or store memory operand

in 16-bit parts (as applicable), one per cycle

rX.S

rX.S op (rY | [rY] | [rY+])

rX.S

rX.S op

rX op q

rX.S

rY.S op ([rZ+I] | [[rZ]] | [[rZ+]] | [rZ+rW.S] | [rZ+I]

| [rZ+[rW].S] | [rZ+[rW+].S])

(address)

General operand types

1) "S" sizes may be different for result and address.

r10

r11

r12

r13

r14 / sp

031

15 7

General registers

([rY+I] | [[rY]] | [[rY+]] | [rY+rZ.S] | [rY+I]

| [rY+[rZ].S] | [rY+[rZ+].S]);

([rY+I] | [[rY]] | [[rY+]] | [rY+rZ.S] | [rY+I]

| [rY+[rZ].S] | [rY+[rZ+].S]);

rX.S

(rY | [rY] | [rY+] | [rY+I] | [[rY]] | [[rY+]] | [rY+rZ.S]

| [rY+I] | [rY+[rZ].S] | [rY+[rZ+].S])

(address)

Figure 3.1: CRIS architecture: overview of parts relevant to GCC

3.1.2 Sizes

Operand sizes are byte, word, and dword, symbolized by b, w and d respectively,

and with (capital) S as any one of that set. Operations on word or byte do not

change the more signiﬁcant parts of the register. For arithmetic on larger data

than dword, a special “extend” ﬂag is used for easy carry-passing.

3.1.3 Addressing modes

Most “binary operator” instructions are two-operand instructions, with one reg-

ister the same as the destination and one of the source operands. The other

operand can be in memory, be a constant or be another register. The basic

addressing-modes are very few: quick immediate, register, indirect register and

indirect register with post-increment, symbolized by q, rX, [rX] and [rX+] re-

spectively. An operand with a basic addressing-mode except q, is denoted with

(lower-case) s. More complex addressing-modes are implemented by special in-

structions called address preﬁx instructions, that modify an s memory operand.

They are called preﬁxed addressing-modes.

The following addressing-modes, interpreted by the assembler, are imple-

mented through address preﬁx instructions:

3.1. THE TARGET ARCHITECTURE 19

Mode description Assembler syntax Comment

Indirect with oﬀset [rX+I ] I is a constant −128 ≤ I ≤ 127

[rX+[rY ].S ]

[rX+[rY+].S] The S is the size of the sign-

extended access and increment

Double indirect [[rX ]]

[[rX+]]

Indirect plus scaled [rX+rY.S ] rY is multiplied by sizeof (S)

(i.e. 1, 2 or 4)

Double indirect is also available in a version with post-increment of rX, mostly

used implicitly by the assembler when rX is pc. This results in addresses of the

form [address], where address is a constant. This is often used for reading and

writing a single global variable in C.

Immediate constants other than what ﬁts in the six bits of a quick immediate

constant, are expressed using indirect post-increment on pc. As a special case,

post-increment on pc for byte operands will cause an increment by two, to keep

pc word-aligned.

3.1.4 Instructions

An opcode is always 16 bits long, counting address preﬁxes as separate instruc-

tions, and non-quick immediate constants as a separate part. For each arith-

metic operation, both the signed and the unsigned condition results is stored in

ccr like with e.g. the Motorola MC68K series.

All logical, arithmetic and move-into-register instructions update the condi-

tion codes, except for addi and the side-eﬀect-part of the preﬁxed addressing-

modes with side-eﬀects (see page 20). Moves into memory do not update the

condition code register. Most condition-code-results reﬂect useful conditions, in

that the condition reﬂects a compare by zero with the result of the operation.

There are some diﬀerences in the CRIS architecture, compared to popular

microprocessor architectures:

• The pc is not saved on the stack at a subroutine call (the jsr instruction).

Rather, it is placed in srp and the called subroutine must take care of

saving this register when needed.

• The branch instructions and the ret return instruction all have a one-

instruction delay before they are executed, a delay-slot. The delay-slot

instruction is located at the address after the branch, and will be executed

before the branch is taken. It must ﬁt completely in 16 bits, so no preﬁxed

The assembler transforms I < −128, I > 127 and symbolic (unknown) I into the

[rX+[rY+].S] form, using pc as rY and word and dword as S. The dword mode was a late

addition before CRIS went silicon, to be used for symbolic expressions unknown at compile

time. Note that the speciﬁc byte form of this instruction, [rX+[rY+].b] (with and without

post-increment), is a diﬀerent address preﬁx instruction than the [rX+I ], where I is known

to be −128 ≤ I ≤ 127.

20 CHAPTER 3. THE TARGET SYSTEM

addressing-mode is possible. It must not use pc in its operands. If no

useful instruction can be scheduled for the delay-slot, a nop instruction

has to be placed there.

• The preﬁxed addressing-modes have an optional assignment side-eﬀect

feature.

This means that you can optionally assign the value of the

eﬀective address to a register. In assembler notation, this is for example

[rY=rX+I ] and [rX=rY+rZ.S ]. Nothing is won if rX and rY are the same

and if only registers are involved; then you could just as well use a separate

addi instruction. The [rX=rX+I ] case still gives one word shorter code

for the case where −128 ≤ I ≤ −64 or 64 ≤ I ≤ 127, since the 8-bit signed

oﬀset is contained within the address preﬁx, and not in an extra word as

it would be with the corresponding add or sub instruction.

• When using the preﬁxed addressing-modes, you can specify three-operand

behavior

for the instruction. Instead of having one register as both being

a source and the destination, you could perform the operation on the reg-

ister and the speciﬁed memory location, and store the result in another

dress r0 plus 42, sign-extend it to dword, add it to r1 and store the result

in r2.

• No multiply or divide instructions. There are two instructions implement-

ing a singe step of multiply and divide, to be used in library functions.

bdap.w [pc+],r3

1234

add.d [r2],r0

biap.d r1,r4

dip [pc+]

foo (low 16 bits of address)

add.d [r2],r2

add.w [r0+],r2

foo (high 16 bits of address)

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Figure 3.2: Preﬁx instructions: placement and assembler expansion

The preﬁx instructions can be expressed explicitly, but in practice they are

never used that way, and will not be described further.

Note that only one of these options is available for each instruction.

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