PIC32MX695f512h: WF121主控SPI接口详解与特性

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本文档主要介绍了Microchip Technology Inc.的PIC32MX695f512H微控制器中的Serial Peripheral Interface (SPI)模块。SPI是一种同步串行通信接口，被广泛应用于与外部设备如EEPROM、移位寄存器、显示器驱动器、ADC（模拟到数字转换器）以及音频编码解码器等进行通信。该模块支持Motorola® SPI和SIOP（Serial Input/Output Protocol）两种标准接口，提供了一种高效且灵活的方式来实现数据交换。第23.1节是介绍，它详细阐述了SPI模块在整体系统中的作用以及其通用特性，强调了它在节省通信线缆和提高系统性能方面的优势。SPI模块通过异步方式工作，允许多个设备同时在总线上发送和接收数据，提高了系统的并发性和效率。第23.2节涵盖了状态和控制寄存器，这部分介绍了如何配置和管理SPI模块的不同工作模式，包括时钟速率、数据线配置、模式选择等，这对于正确设置和操作SPI通信至关重要。第23.3节讨论了SPI的工作模式，如全双工、主/从模式以及模式0-3，每种模式都有其特定的应用场景和协议细节，开发者需要根据具体需求选择合适的模式。第23.4节涉及音频协议接口模式，可能涉及到音频编解码器的特殊配置，展示了SPI在音频应用中的高级功能。第23.5节深入解析了中断机制，包括中断触发条件、中断处理和中断屏蔽，确保了在数据传输过程中能够及时响应外部事件。第23.6节探讨了SPI在节能和调试模式下的操作，这涉及到如何优化电源管理以延长电池寿命或者在开发过程中利用调试功能进行有效的硬件调试。第23.7节关注不同复位条件下SPI模块的行为，确保了系统重启后通信的稳定性。第23.8节提到了使用SPI模块的周边器件，包括这些器件如何与SPI模块配合工作，以实现更复杂的功能和系统集成。最后，第23.9节链接了一些相关的应用笔记，提供了实际项目中的设计建议和技术支持，对于解决实际问题具有参考价值。第23.10节是修订历史，记录了SPI模块的更新和改进，以便用户了解最新版本的功能和改进。总结来说，这篇文档详尽地讲解了如何在PIC32MX695f512H上有效地利用SPI模块进行串行通信，无论是基本配置还是高级应用，都为开发人员提供了丰富的资源和指导。

PIC32 Family Reference Manual

bit 5 MSTEN: Master Mode Enable bit

1 = Master mode

0 = Slave mode

bit 4 DISSDI: Disable SDI bit

1 = SDIx pin is not used by the SPI module (pin is controlled by PORT function)

0 = SDIx pin is controlled by the SPI module

bit 3-2 STXISEL<1:0>: SPI Transmit Buffer Empty Interrupt Mode bits

(1,3)

11 = SPIxTXIF is set when the buffer is not full (has one or more empty elements)

10 = SPIxTXIF is set when the buffer is empty by one-half or more

01 = SPIxTXIF is set when the buffer is completely empty

00 = SPIxTXIF is set when the last transfer is shifted out of SPISR and transmit operations are

complete

bit 1-0 SRXISEL<1:0>: SPI Receive Buffer Full Interrupt Mode bits

(1,3)

11 = SPIxRXIF is set when the buffer is full

10 = SPIxRXIF is set when the buffer is full by one-half or more

01 = SPIxRXIF is set when the buffer is not empty

00 = SPIxRXIF is set when the last word in the receive buffer is read (i.e., buffer is empty)

Note 1: These bits are not available on all devices. Refer to the specific device data sheet for availability.

2: When FRMEN = 1, the MSSEN bit is not used.

3: Valid only when enhanced buffers are enabled (ENHBUF = 1).

Section 23. Serial Peripheral Interface (SPI)

Serial Peripheral

Interface (SPI)

Bit

Range

Bit

31/23/15/7

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

Bit

24/16/8/0

31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

23:16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

15:8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-1 R/W-0 R/W-0

SPISGNEXT — — FRMERREN SPIROVEN SPITUREN IGNROV IGNTUR

7:0

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

AUDEN

(1,3)

— — — AUDMONO

(2)

— AUDMOD<1:0>

(2,4)

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Write ‘0’; ignore read

bit 15 SPISGNEXT: Sign Extend Read Data from the RX FIFO bit

1 = Data from RX FIFO is sign extended

0 = Data from RX FIFO is not sign extened

bit 14-13 Unimplemented: Write ‘0’; ignore read

bit 12 FRMERREN: Enable Interrupt Events via FRMERR bit

1 = Frame Error overflow generates error interrupts

0 = Frame Error does not generate error interrupts

bit 11 SPIROVEN: Enable Interrupt Events via SPIROV bit

1 = Receive overflow generates error interrupts

0 = Receive overflow does not generate error interrupts

bit 10 SPITUREN: Enable Interrupt Events via SPITUR bit

1 = Transmit Underrun generates error interrupts

0 = Transmit Underrun does not generate error interrupts

bit 9 IGNROV: Ignore Receive Overflow bit (for Audio Data Transmissions)

1 = A ROV is not a critical error; during ROV data in the FIFO is not overwritten by receive data

0 = A ROV is a critical error which stop SPI operation

bit 8 IGNTUR: Ignore Transmit Underrun bit (for Audio Data Transmissions)

1 = A TUR is not a critical error and zeros are transmitted until the SPIxTXB is not empty

0 = A TUR is a critical error which stop SPI operation

bit 7 AUDEN: Enable Audio CODEC Support bit

(1,3)

1 = Audio protocol enabled

0 = Audio protocol disabled

bit 6-5 Unimplemented: Write ‘0’; ignore read

Note 1: This bit can only be written when the ON bit = 0.

2: This bit can only be written when the ON bit = 0, and is only valid for AUDEN = 1.

3: When Audio mode is enabled (i.e., AUDEN = 1), the following bits in the SPIxCON register are configured

by the module internally:

• The direction of the Bit Clock (BCLK) and Left/Right Channel Clock (LRCK) are selected based on the

MSTEN bit

•FRMEN = 1, FRMCNT = 1, SMP = 0

• In Slave mode (MSTN = 0, FRMSYNC = 1) and in Master mode MSTN = 1, FRMSYNC = 0

4: In I

S mode, SPIFE = 0, in Right or Left-Justified mode, SPIFE = 1, except in DSP/PCM mode when

FRMSYPW = 0.

5: This feature is not available on all devices. Refer to the specific device data sheet for availability.

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