0018-9162/02/$17.00 © 2002 IEEE70 Computer
Networks on Chips:
A New SoC
Paradigm
S
ystem-on-chip (SoC) designs provide inte-
grated solutions to challenging design
problems in the telecommunications, mul-
timedia, and consumer electronics do-
mains. Much of the progress in these fields
hinges on the designers’ ability to conceive complex
electronic engines under strong time-to-market
pressure. Success will rely on using appropriate
design and process technologies, as well as on the
ability to interconnect existing components—
including processors, controllers, and memory
arrays—reliably, in a plug-and-play fashion.
By the end of the decade, SoCs, using 50-nm tran-
sistors operating below one volt, will grow to 4 bil-
lion transistors running at 10 GHz, according to the
International Technology Roadmap for Semicon-
ductors. The major challenge designers of these sys-
tems must overcome will be to provide for function-
ally correct, reliable operation of the interacting com-
ponents. On-chip physical interconnections will pre-
sent a limiting factor for performance and, possibly,
energy consumption.
Silicon technologies face other challenges.
Synchronization of future chips with a single clock
source and negligible skew will be extremely diffi-
cult, if not impossible. The most likely synchro-
nization paradigm for future chips—globally
asynchronous and locally synchronous—involves
using many different clocks. In the absence of a sin-
gle timing reference, SoC chips become distributed
systems on a single silicon substrate. Global con-
trol of the information traffic is unlikely to succeed
because the system needs to keep track of each com-
ponent’s states. Thus, components will initiate data
transfers autonomously, according to their needs.
The global communication pattern will be fully dis-
tributed, with little or no global coordination.
As SoC complexity scales, capturing the system’s
functionality with fully deterministic operation
models will become increasingly difficult. As global
wires span multiple clock domains, synchroniza-
tion failures in communicating between different
domains will be rare but unavoidable events.
1
Moreover, energy and device reliability concerns
will impose small logic swings and power supplies,
most likely less than one volt. Electrical noise due
to crosstalk, electromagnetic interference, and radi-
ation-induced charge injection will likely produce
data errors, also called upsets. Thus, transmitting
digital values on wires will be inherently unreliable
and nondeterministic. Other causes of nondeter-
minism include design components with a high level
of abstraction and coarse granularity and distrib-
uted communication control.
Focusing on using probabilistic metrics such as
average values or variance to quantify design objec-
tives such as performance and power will lead to a
major change in design methodologies. Overall,
SoC design will be based on both deterministic and
stochastic models. Creating complex SoCs requires
a modular, component-based approach to both
hardware and software design.
Based on the premise that interconnect technology
will be the limiting factor for achieving SoCs’ opera-
tional goals, we postulate that the layered design of
reconfigurable micronetworks, which exploits the
methods and tools used for general networks, can
best achieve efficient communication on SoCs.
On-chip micronetworks, designed with a layered methodology, will
meet the distinctive challenges of providing functionally correct,
reliable operation of interacting system-on-chip components.
Luca Benini
University of
Bologna
Giovanni
De Micheli
Stanford University
SOC DESIGNS