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Freescale MC9S08AW60 单片机技术手册更新
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"MC9S08AW60.pdf 是Freescale半导体公司关于08系列MC9S08AW60单片机的技术手册补充文档,内容涉及到从黄金线到铜线封装的转变,以及相关器件的更新包装信息。这份文档提供了旧版(黄金线)与新版(铜线)封装的对比表格,并指示用户如何在Freescale官网上查找新包装的图纸。此外,还提到了QFN封装的电气连接推荐指南EB806,用于指导设备的暴露垫上的电气连接建议。"
MC9S08AW60是一款由Freescale Semiconductor生产的微控制器,属于08系列。这份技术手册的补充部分主要关注的是产品封装的变化,由于某些封装从黄金线改为铜线,导致了封装外形编号的变更。这些更改是为了适应技术的发展和改进,比如提高生产效率、降低成本或者改善电气性能。
在文档中列出的表格里,可以看到不同型号的微控制器,如MC9S08AC16、MC9S08GB60A等,它们的原有(黄金线)封装文档编号与当前(铜线)封装文档编号的对应关系。例如,MC9S08AW60的旧版包装文档编号是98ARH99048A,而新版则是98ASA00466D。如果开发者或工程师需要查看新的封装设计,他们可以通过访问Freescale的官方网站,搜索新的98A封装编号来获取详细信息。
此外,文档还提及了QFN(Quad Flat No-Lead,无引脚四方扁平封装)的使用指南EB806,该指南对于理解QFN和DFN(Dual Flat No-Lead,双面无引脚扁平封装)设备的暴露垫上的电气连接具有重要意义。这包括了在使用QFN封装时,如何确保正确且安全的电气连接,以防止潜在的热管理问题和信号完整性问题。
总结起来,这份MC9S08AW60的技术手册补充文档是开发和设计过程中不可或缺的参考资料,它提供了关键的封装更新信息,帮助工程师们适应新的制造标准,同时保证设计的兼容性和可靠性。对于使用或计划使用MC9S08AW60及其相关型号的单片机的开发者来说,了解这些变更和建议是非常重要的。
MC9S08AW60 Data Sheet, Rev 2
14 Freescale Semiconductor
Section Number Title Page
10.4.3 Timer x Counter Modulo Registers (TPMxMODH:TPMxMODL) .............................172
10.4.4 Timer x Channel n Status and Control Register (TPMxCnSC) ....................................173
10.4.5 Timer x Channel Value Registers (TPMxCnVH:TPMxCnVL) ....................................174
10.5 Functional Description ..................................................................................................................175
10.5.1 Counter .........................................................................................................................175
10.5.2 Channel Mode Selection ...............................................................................................176
10.5.3 Center-Aligned PWM Mode ........................................................................................178
10.6 TPM Interrupts ..............................................................................................................................179
10.6.1 Clearing Timer Interrupt Flags .....................................................................................179
10.6.2 Timer Overflow Interrupt Description ..........................................................................179
10.6.3 Channel Event Interrupt Description ............................................................................180
10.6.4 PWM End-of-Duty-Cycle Events .................................................................................180
Chapter 11
Serial Communications Interface (S08SCIV2)
11.1 Introduction ...................................................................................................................................181
11.1.1 Features .........................................................................................................................183
11.1.2 Modes of Operation ......................................................................................................183
11.1.3 Block Diagram ..............................................................................................................183
11.2 Register Definition ........................................................................................................................185
11.2.1 SCI Baud Rate Registers (SCIxBDH, SCIxBHL) ........................................................186
11.2.2 SCI Control Register 1 (SCIxC1) .................................................................................187
11.2.3 SCI Control Register 2 (SCIxC2) .................................................................................188
11.2.4 SCI Status Register 1 (SCIxS1) ....................................................................................189
11.2.5 SCI Status Register 2 (SCIxS2) ....................................................................................191
11.2.6 SCI Control Register 3 (SCIxC3) .................................................................................191
11.2.7 SCI Data Register (SCIxD) ..........................................................................................192
11.3 Functional Description ..................................................................................................................192
11.3.1 Baud Rate Generation ...................................................................................................193
11.3.2 Transmitter Functional Description ..............................................................................193
11.3.3 Receiver Functional Description ..................................................................................194
11.3.4 Interrupts and Status Flags ...........................................................................................196
11.3.5 Additional SCI Functions .............................................................................................197
Chapter 12
Serial Peripheral Interface (S08SPIV3)
12.0.1 Features .........................................................................................................................201
12.0.2 Block Diagrams ............................................................................................................201
12.0.3 SPI Baud Rate Generation ............................................................................................203
12.1 External Signal Description ..........................................................................................................204
12.1.1 SPSCK — SPI Serial Clock .........................................................................................204
12.1.2 MOSI — Master Data Out, Slave Data In ....................................................................204
MC9S08AW60 Data Sheet, Rev 2
Freescale Semiconductor 15
Section Number Title Page
12.1.3 MISO — Master Data In, Slave Data Out ....................................................................204
12.1.4
SS — Slave Select ........................................................................................................204
12.2 Modes of Operation .......................................................................................................................205
12.2.1 SPI in Stop Modes ........................................................................................................205
12.3 Register Definition ........................................................................................................................205
12.3.1 SPI Control Register 1 (SPI1C1) ..................................................................................205
12.3.2 SPI Control Register 2 (SPI1C2) ..................................................................................206
12.3.3 SPI Baud Rate Register (SPI1BR) ...............................................................................207
12.3.4 SPI Status Register (SPI1S) ..........................................................................................208
12.3.5 SPI Data Register (SPI1D) ...........................................................................................209
12.4 Functional Description ..................................................................................................................210
12.4.1 SPI Clock Formats ........................................................................................................210
12.4.2 SPI Interrupts ................................................................................................................213
12.4.3 Mode Fault Detection ...................................................................................................213
Chapter 13
Inter-Integrated Circuit (S08IICV1)
13.1 Introduction ...................................................................................................................................215
13.1.1 Features .........................................................................................................................217
13.1.2 Modes of Operation ......................................................................................................217
13.1.3 Block Diagram ..............................................................................................................218
13.2 External Signal Description ..........................................................................................................218
13.2.1 SCL — Serial Clock Line .............................................................................................218
13.2.2 SDA — Serial Data Line ..............................................................................................218
13.3 Register Definition ........................................................................................................................218
13.3.1 IIC Address Register (IIC1A) .......................................................................................219
13.3.2 IIC Frequency Divider Register (IIC1F) ......................................................................219
13.3.3 IIC Control Register (IIC1C) ........................................................................................222
13.3.4 IIC Status Register (IIC1S) ..........................................................................................223
13.3.5 IIC Data I/O Register (IIC1D) ......................................................................................224
13.4 Functional Description ..................................................................................................................225
13.4.1 IIC Protocol ..................................................................................................................225
13.5 Resets ............................................................................................................................................228
13.6 Interrupts .......................................................................................................................................228
13.6.1 Byte Transfer Interrupt .................................................................................................229
13.6.2 Address Detect Interrupt ...............................................................................................229
13.6.3 Arbitration Lost Interrupt .............................................................................................229
13.7 Initialization/Application Information ..........................................................................................230
MC9S08AW60 Data Sheet, Rev 2
16 Freescale Semiconductor
Section Number Title Page
Chapter 14
Analog-to-Digital Converter (S08ADC10V1)
14.1 Overview .......................................................................................................................................233
14.2 Channel Assignments ....................................................................................................................233
14.2.1 Alternate Clock .............................................................................................................234
14.2.2 Hardware Trigger ..........................................................................................................234
14.2.3 Temperature Sensor ......................................................................................................235
14.2.4 Features .........................................................................................................................237
14.2.5 Block Diagram ..............................................................................................................237
14.3 External Signal Description ..........................................................................................................238
14.3.1 Analog Power (V
DDAD
) ................................................................................................239
14.3.2 Analog Ground (V
SSAD
) ..............................................................................................239
14.3.3 Voltage Reference High (V
REFH
) .................................................................................239
14.3.4 Voltage Reference Low (V
REFL
) ..................................................................................239
14.3.5 Analog Channel Inputs (ADx) ......................................................................................239
14.4 Register Definition ........................................................................................................................239
14.4.1 Status and Control Register 1 (ADC1SC1) ..................................................................239
14.4.2 Status and Control Register 2 (ADC1SC2) ..................................................................241
14.4.3 Data Result High Register (ADC1RH) ........................................................................242
14.4.4 Data Result Low Register (ADC1RL) ..........................................................................242
14.4.5 Compare Value High Register (ADC1CVH) ................................................................243
14.4.6 Compare Value Low Register (ADC1CVL) .................................................................243
14.4.7 Configuration Register (ADC1CFG) ............................................................................243
14.4.8 Pin Control 1 Register (APCTL1) ................................................................................245
14.4.9 Pin Control 2 Register (APCTL2) ................................................................................246
14.4.10 Pin Control 3 Register (APCTL3) ................................................................................247
14.5 Functional Description ..................................................................................................................248
14.5.1 Clock Select and Divide Control ..................................................................................248
14.5.2 Input Select and Pin Control .........................................................................................249
14.5.3 Hardware Trigger ..........................................................................................................249
14.5.4 Conversion Control .......................................................................................................249
14.5.5 Automatic Compare Function ......................................................................................252
14.5.6 MCU Wait Mode Operation .........................................................................................252
14.5.7 MCU Stop3 Mode Operation .......................................................................................252
14.5.8 MCU Stop1 and Stop2 Mode Operation ......................................................................253
14.6 Initialization Information ..............................................................................................................253
14.6.1 ADC Module Initialization Example ...........................................................................253
14.7 Application Information ................................................................................................................255
14.7.1 External Pins and Routing ............................................................................................255
14.7.2 Sources of Error ............................................................................................................257
MC9S08AW60 Data Sheet, Rev 2
Freescale Semiconductor 17
Section Number Title Page
Chapter 15
Development Support
15.1 Introduction ...................................................................................................................................261
15.1.1 Features .........................................................................................................................262
15.2 Background Debug Controller (BDC) ..........................................................................................262
15.2.1 BKGD Pin Description .................................................................................................263
15.2.2 Communication Details ................................................................................................264
15.2.3 BDC Commands ...........................................................................................................268
15.2.4 BDC Hardware Breakpoint ..........................................................................................270
15.3 On-Chip Debug System (DBG) ....................................................................................................271
15.3.1 Comparators A and B ...................................................................................................271
15.3.2 Bus Capture Information and FIFO Operation .............................................................271
15.3.3 Change-of-Flow Information ........................................................................................272
15.3.4 Tag vs. Force Breakpoints and Triggers .......................................................................272
15.3.5 Trigger Modes ..............................................................................................................273
15.3.6 Hardware Breakpoints ..................................................................................................275
15.4 Register Definition ........................................................................................................................275
15.4.1 BDC Registers and Control Bits ...................................................................................275
15.4.2 System Background Debug Force Reset Register (SBDFR) ........................................277
15.4.3 DBG Registers and Control Bits ..................................................................................278
Appendix A
Electrical Characteristics and Timing Specifications
A.1 Introduction ....................................................................................................................................283
A.2 Parameter Classification.................................................................................................................283
A.3 Absolute Maximum Ratings...........................................................................................................283
A.4 Thermal Characteristics..................................................................................................................285
A.5 ESD Protection and Latch-Up Immunity .......................................................................................286
A.6 DC Characteristics..........................................................................................................................287
A.7 Supply Current Characteristics.......................................................................................................291
A.8 ADC Characteristics.......................................................................................................................293
A.9 Internal Clock Generation Module Characteristics........................................................................296
A.9.1 ICG Frequency Specifications.......................................................................................297
A.10 AC Characteristics..........................................................................................................................300
A.10.1 Control Timing ..............................................................................................................300
A.10.2 Timer/PWM (TPM) Module Timing.............................................................................302
A.11 SPI Characteristics .........................................................................................................................303
A.12 FLASH Specifications....................................................................................................................306
A.13 EMC Performance..........................................................................................................................307
A.13.1 Radiated Emissions .......................................................................................................307
A.13.2 Conducted Transient Susceptibility...............................................................................307
MC9S08AW60 Data Sheet, Rev 2
18 Freescale Semiconductor
Section Number Title Page
Appendix B
Ordering Information and Mechanical Drawings
B.1 Ordering Information .....................................................................................................................309
B.2 Orderable Part Numbering System ................................................................................................310
B.2.1 Consumer and Industrial Orderable Part Numbering System .......................................310
B.2.2 Automotive Orderable Part Numbering System............................................................310
B.3 Mechanical Drawings.....................................................................................................................310
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