第八版《计算机组成与体系结构(性能设计)》完整答案解析

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"这是一份关于《计算机组成与体系结构(性能设计)》第八版的完整答案手册，由威廉·斯托林斯(William Stallings)编写。该手册包含了书中复习问题和作业题的答案，旨在帮助读者深入理解和掌握计算机组织与架构的相关知识。" 在《计算机组成与体系结构(性能设计)》这本书中，作者William Stallings探讨了计算机系统的基础以及如何设计出高性能的计算机系统。以下是各个章节的主要知识点： 1. **Chapter 1 Introduction** - 这一章通常会介绍计算机系统的基本概念，包括计算机的五大部分（运算器、控制器、存储器、输入设备和输出设备），以及计算机体系结构的基本原理，如冯·诺依曼结构。 2. **Chapter 2 Computer Evolution and Performance** - 本章涵盖了计算机的发展历程，从早期的机械计算机到现代的微处理器，同时讨论了衡量计算机性能的关键指标，如时钟速度、 MIPS（每秒百万指令数）和浮点运算性能。 3. **Chapter 3 Computer Function and Interconnection** - 讲解计算机内部各部件的功能和它们之间的通信方式，包括总线、接口和系统互连技术，以及如何通过这些技术提高系统的数据传输效率。 4. **Chapter 4 Cache Memory** - 针对高速缓存（Cache）的工作原理进行深入讲解，包括缓存层次结构、替换策略（如LRU, FIFO等）、命中率计算以及缓存对程序性能的影响。 5. **Chapter 5 Internal Memory** - 详细介绍内存的类型，如RAM（随机存取存储器）和ROM（只读存储器），以及动态随机存取存储器（DRAM）和静态随机存取存储器（SRAM）的区别，还包括内存的组织结构和地址映射。 6. **Chapter 6 External Memory** - 讨论外部存储器，如硬盘、固态驱动器（SSD）和光盘，以及磁盘I/O操作、磁盘调度算法和虚拟内存的概念。 7. **Chapter 7 Input/Output (I/O)** - 深入探讨输入输出设备的原理，包括中断、DMA（直接内存访问）和端口映射I/O，以及各种I/O控制方式对系统性能的影响。这本书的解决方案手册提供了对这些问题的解答，有助于学生或自学者检查自己的理解程度，并进一步提升对计算机系统复杂性的认识。同时，作者鼓励读者发现并报告错误，以保持资料的准确性。对于学习计算机组成与体系结构的人来说，这份手册是宝贵的参考资料，它不仅可以帮助解决课后习题，还能作为深入研究和复习的重要工具。

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a "column" in memory. In addition to the two-step address operation, the

microprocessor will need 2 cycles to fetch the 32 bit instruction/operand.

c. The program counter must be at least 24 bits. Typically, a 32-bit microprocessor

will have a 32-bit external address bus and a 32-bit program counter, unless on-

chip segment registers are used that may work with a smaller program counter.

If the instruction register is to contain the whole instruction, it will have to be

32-bits long; if it will contain only the op code (called the op code register) then

it will have to be 8 bits long.

3.4 In cases (a) and (b), the microprocessor will be able to access 2

= 64K bytes; the

only difference is that with an 8-bit memory each access will transfer a byte, while

with a 16-bit memory an access may transfer a byte or a 16-byte word. For case (c),

separate input and output instructions are needed, whose execution will generate

separate "I/O signals" (different from the "memory signals" generated with the

execution of memory-type instructions); at a minimum, one additional output pin

will be required to carry this new signal. For case (d), it can support 2

= 256 input

and 2

= 256 output byte ports and the same number of input and output 16-bit

ports; in either case, the distinction between an input and an output port is defined

by the different signal that the executed input or output instruction generated.

3.5 Clock cycle =

8 MHz

= 125 ns

Bus cycle = 4 × 125 ns = 500 ns

2 bytes transferred every 500 ns; thus transfer rate = 4 MBytes/sec

Doubling the frequency may mean adopting a new chip manufacturing technology

(assuming each instructions will have the same number of clock cycles); doubling

the external data bus means wider (maybe newer) on-chip data bus

drivers/latches and modifications to the bus control logic. In the first case, the

speed of the memory chips will also need to double (roughly) not to slow down

the microprocessor; in the second case, the "wordlength" of the memory will have

to double to be able to send/receive 32-bit quantities.

3.6 a. Input from the Teletype is stored in INPR. The INPR will only accept data from

the Teletype when FGI=0. When data arrives, it is stored in INPR, and FGI is

set to 1. The CPU periodically checks FGI. If FGI =1, the CPU transfers the

contents of INPR to the AC and sets FGI to 0.

When the CPU has data to send to the Teletype, it checks FGO. If FGO = 0,

the CPU must wait. If FGO = 1, the CPU transfers the contents of the AC to

OUTR and sets FGO to 0. The Teletype sets FGI to 1 after the word is printed.

b. The process described in (a) is very wasteful. The CPU, which is much faster

than the Teletype, must repeatedly check FGI and FGO. If interrupts are used,

the Teletype can issue an interrupt to the CPU whenever it is ready to accept or

send data. The IEN register can be set by the CPU (under programmer control)

3.7 a. During a single bus cycle, the 8-bit microprocessor transfers one byte while the

16-bit microprocessor transfers two bytes. The 16-bit microprocessor has twice

the data transfer rate.

b. Suppose we do 100 transfers of operands and instructions, of which 50 are one

byte long and 50 are two bytes long. The 8-bit microprocessor takes 50 + (2 x

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50) = 150 bus cycles for the transfer. The 16-bit microprocessor requires 50 + 50

= 100 bus cycles. Thus, the data transfer rates differ by a factor of 1.5.

3.8 The whole point of the clock is to define event times on the bus; therefore, we wish

for a bus arbitration operation to be made each clock cycle. This requires that the

priority signal propagate the length of the daisy chain (Figure 3.26) in one clock

period. Thus, the maximum number of masters is determined by dividing the

amount of time it takes a bus master to pass through the bus priority by the clock

period.

3.9 The lowest-priority device is assigned priority 16. This device must defer to all the

others. However, it may transmit in any slot not reserved by the other SBI devices.

3.10 At the beginning of any slot, if none of the TR lines is asserted, only the priority 16

device may transmit. This gives it the lowest average wait time under most

circumstances. Only when there is heavy demand on the bus, which means that

most of the time there is at least one pending request, will the priority 16 device

not have the lowest average wait time.

3.11 a. With a clocking frequency of 10 MHz, the clock period is 10

–9

s = 100 ns. The

length of the memory read cycle is 300 ns.

b. The Read signal begins to fall at 75 ns from the beginning of the third clock

cycle (middle of the second half of T

). Thus, memory must place the data on

the bus no later than 55 ns from the beginning of T

3.12 a. The clock period is 125 ns. Therefore, two clock cycles need to be inserted.

b. From Figure 3.19, the Read signal begins to rise early in T

. To insert two clock

cycles, the Ready line can be put in low at the beginning of T

and kept low for

250 ns.

3.13 a. A 5 MHz clock corresponds to a clock period of 200 ns. Therefore, the Write

signal has a duration of 150 ns.

b. The data remain valid for 150 + 20 = 170 ns.

c. One wait state.

3.14 a. Without the wait states, the instruction takes 16 bus clock cycles. The

instruction requires four memory accesses, resulting in 8 wait states. The

instruction, with wait states, takes 24 clock cycles, for an increase of 50%.

b. In this case, the instruction takes 26 bus cycles without wait states and 34 bus

cycles with wait states, for an increase of 33%.

3.15 a. The clock period is 125 ns. One bus read cycle takes 500 ns = 0.5 µs. If the bus

cycles repeat one after another, we can achieve a data transfer rate of 2 MB/s.

b. The wait state extends the bus read cycle by 125 ns, for a total duration of 0.625

µs. The corresponding data transfer rate is 1/0.625 = 1.6 MB/s.

3.16 A bus cycle takes 0.25 µs, so a memory cycle takes 1 µs. If both operands are even-

aligned, it takes 2 µs to fetch the two operands. If one is odd-aligned, the time

required is 3 µs. If both are odd-aligned, the time required is 4 µs.

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CHAPTER 4 CACHE MEMORY

NSWERS TO

UESTIONS

4.1 Sequential access: Memory is organized into units of data, called records. Access

must be made in a specific linear sequence. Direct access: Individual blocks or

records have a unique address based on physical location. Access is accomplished

by direct access to reach a general vicinity plus sequential searching, counting, or

waiting to reach the final location. Random access: Each addressable location in

memory has a unique, physically wired-in addressing mechanism. The time to

access a given location is independent of the sequence of prior accesses and is

constant.

4.2 Faster access time, greater cost per bit; greater capacity, smaller cost per bit; greater

capacity, slower access time.

4.3 It is possible to organize data across a memory hierarchy such that the percentage

of accesses to each successively lower level is substantially less than that of the

level above. Because memory references tend to cluster, the data in the higher-

level memory need not change very often to satisfy memory access requests.

4.4 In a cache system, direct mapping maps each block of main memory into only one

possible cache line. Associative mapping permits each main memory block to be

loaded into any line of the cache. In set-associative mapping, the cache is divided

into a number of sets of cache lines; each main memory block can be mapped into

any line in a particular set.

4.5 One field identifies a unique word or byte within a block of main memory. The

remaining two fields specify one of the blocks of main memory. These two fields

are a line field, which identifies one of the lines of the cache, and a tag field, which

identifies one of the blocks that can fit into that line.

4.6 A tag field uniquely identifies a block of main memory. A word field identifies a

unique word or byte within a block of main memory.

4.7 One field identifies a unique word or byte within a block of main memory. The

remaining two fields specify one of the blocks of main memory. These two fields

are a set field, which identifies one of the sets of the cache, and a tag field, which

identifies one of the blocks that can fit into that set.

4.8 Spatial locality refers to the tendency of execution to involve a number of memory

locations that are clustered. Temporal locality refers to the tendency for a

processor to access memory locations that have been used recently.

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4.9 Spatial locality is generally exploited by using larger cache blocks and by

incorporating prefetching mechanisms (fetching items of anticipated use) into the

cache control logic. Temporal locality is exploited by keeping recently used

instruction and data values in cache memory and by exploiting a cache hierarchy.

NSWERS TO

ROBLEMS

4.1 The cache is divided into 16 sets of 4 lines each. Therefore, 4 bits are needed to

identify the set number. Main memory consists of 4K = 2

blocks. Therefore, the

set plus tag lengths must be 12 bits and therefore the tag length is 8 bits. Each

block contains 128 words. Therefore, 7 bits are needed to specify the word.

TAG

SET

WORD

Main memory address =

4.2 There are a total of 8 kbytes/16 bytes = 512 lines in the cache. Thus the cache

consists of 256 sets of 2 lines each. Therefore 8 bits are needed to identify the set

number. For the 64-Mbyte main memory, a 26-bit address is needed. Main memory

consists of 64-Mbyte/16 bytes = 2

blocks. Therefore, the set plus tag lengths must

be 22 bits, so the tag length is 14 bits and the word field length is 4 bits.

TAG

SET

WORD

Main memory address =

4.3

Address

111111

666666

BBBBBB

a. Tag/Line/Word

11/444/1

66/1999/2

BB/2EEE/3

b. Tag /Word

44444/1

199999/2

2EEEEE/3

c. Tag/Set/Word

22/444/1

CC/1999/2

177/EEE/3

4.4 a. Address length: 24; number of addressable units: 2

; block size: 4; number of

blocks in main memory: 2

; number of lines in cache: 2

; size of tag: 8.

b. Address length: 24; number of addressable units: 2

; block size: 4; number of

blocks in main memory: 2

; number of lines in cache: 4000 hex; size of tag: 22.

c. Address length: 24; number of addressable units: 2

; block size: 4; number of

blocks in main memory: 2

; number of lines in set: 2; number of sets: 2

;

number of lines in cache: 2

; size of tag: 9.

4.5 Block frame size = 16 bytes = 4 doublewords

Number of block frames in cache =

16 KBytes

16 Bytes

= 1024

Number of sets =

Number of block frames

Associativity

1024

= 256 sets

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