i.MX 6Dual/6Quad：高性能低功耗多媒体应用处理器

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i.MX 6Dual/6Quad Applications Processors for Consumer Products, Rev. 6, 11/2018

16 NXP Semiconductors

Modules List

ROM

96 KB

Boot ROM Internal

Memory

Supports secure and regular Boot Modes. Includes read protection on 4K

region for content protection

ROMCP ROM Controller with

Patch

Data Path ROM Controller with ROM Patch support

SATA Serial ATA Connectivity

Peripherals

The SATA controller and PHY is a complete mixed-signal IP solution

designed to implement SATA II, 3.0 Gbps HDD connectivity.

SDMA Smart Direct Memory

Access

System

Control

Peripherals

The SDMA is multi-channel flexible DMA engine. It helps in maximizing

system performance by off-loading the various cores in dynamic data

routing. It has the following features:

• Powered by a 16-bit Instruction-Set micro-RISC engine

• Multi-channel DMA supporting up to 32 time-division multiplexed DMA

channels

• 48 events with total flexibility to trigger any combination of channels

• Memory accesses including linear, FIFO, and 2D addressing

• Shared peripherals between Arm and SDMA

• Very fast context-switching with 2-level priority based preemptive

multi-tasking

• DMA units with auto-flush and prefetch capability

• Flexible address management for DMA transfers (increment,

decrement, and no address changes on source and destination

address)

• DMA ports can handle unit-directional and bi-directional flows (copy

mode)

• Up to 8-word buffer for configurable burst transfers

• Support of byte-swapping and CRC calculations

• Library of Scripts and API is available

SJC System JTAG

Controller

System

Control

Peripherals

The SJC provides JTAG interface, which complies with JTAG TAP

standards, to internal logic. The i.MX 6Dual/6Quad processors use JTAG

port for production, testing, and system debugging. In addition, the SJC

provides BSR (Boundary Scan Register) standard support, which

complies with IEEE1149.1 and IEEE1149.6 standards.

The JTAG port must be accessible during platform initial laboratory

bring-up, for manufacturing tests and troubleshooting, as well as for

software debugging by authorized entities. The i.MX 6Dual/6Quad SJC

incorporates three security modes for protecting against unauthorized

accesses. Modes are selected through eFUSE configuration.

SNVS Secure Non-Volatile

Storage

Security Secure Non-Volatile Storage, including Secure Real Time Clock, Security

State Machine, Master Key Control, and Violation/Tamper Detection and

reporting.

SPDIF Sony Philips Digital

Interconnect Format

Multimedia

Peripherals

A standard audio file transfer format, developed jointly by the Sony and

Phillips corporations. It supports Transmitter and Receiver functionality.

Table 2. i.MX 6Dual/6Quad Modules List (continued)

Block

Mnemonic

Block Name Subsystem Brief Description

Modules List

i.MX 6Dual/6Quad Applications Processors for Consumer Products, Rev. 6, 11/2018

NXP Semiconductors 17

SSI-1

SSI-2

SSI-3

I2S/SSI/AC97

Interface

Connectivity

Peripherals

The SSI is a full-duplex synchronous interface, which is used on the

processor to provide connectivity with off-chip audio peripherals. The SSI

supports a wide variety of protocols (SSI normal, SSI network, I2S, and

AC-97), bit depths (up to 24 bits per word), and clock / frame sync options.

The SSI has two pairs of 8x24 FIFOs and hardware support for an

external DMA controller to minimize its impact on system performance.

The second pair of FIFOs provides hardware interleaving of a second

audio stream that reduces CPU overhead in use cases where two time

slots are being used simultaneously.

TEMPMON Temperature Monitor System

Control

Peripherals

The temperature monitor/sensor IP module for detecting high temperature

conditions. The temperature read out does not reflect case or ambient

temperature. It reflects the temperature in proximity of the sensor location

on the die. Temperature distribution may not be uniformly distributed;

therefore, the read out value may not be the reflection of the temperature

value for the entire die.

TZASC Trust-Zone Address

Space Controller

Security The TZASC (TZC-380 by Arm) provides security address region control

functions required for intended application. It is used on the path to the

DRAM controller.

UART-1

UART-2

UART-3

UART-4

UART-5

UART Interface Connectivity

Peripherals

Each of the UARTv2 modules support the following serial data

transmit/receive protocols and configurations:

• 7- or 8-bit data words, 1 or 2 stop bits, programmable parity (even, odd

or none)

• Programmable baud rates up to 5 MHz

• 32-byte FIFO on Tx and 32 half-word FIFO on Rx supporting auto-baud

• IrDA 1.0 support (up to SIR speed of 115200 bps)

• Option to operate as 8-pins full UART, DCE, or DTE

USBOH3A USB 2.0 High Speed

OTG and 3x HS

Hosts

Connectivity

Peripherals

USBOH3 contains:

• One high-speed OTG module with integrated HS USB PHY

• One high-speed Host module with integrated HS USB PHY

• Two identical high-speed Host modules connected to HSIC USB ports.

Table 2. i.MX 6Dual/6Quad Modules List (continued)

Block

Mnemonic

Block Name Subsystem Brief Description

i.MX 6Dual/6Quad Applications Processors for Consumer Products, Rev. 6, 11/2018

18 NXP Semiconductors

Modules List

uSDHC-1

uSDHC-2

uSDHC-4

SD/MMC and SDXC

Enhanced

Multi-Media Card /

Secure Digital Host

Controller

Connectivity

Peripherals

i.MX 6Dual/6Quad specific SoC characteristics:

All four MMC/SD/SDIO controller IPs are identical and are based on the

uSDHC IP. They are:

• Conforms to the SD Host Controller Standard Specification version 3.0

• Fully compliant with MMC command/response sets and Physical Layer

as defined in the Multimedia Card System Specification,

v4.2/4.3/4.4/4.41 including high-capacity (size > 2 GB) cards HC MMC.

Hardware reset as specified for eMMC cards is supported at ports #3

and #4 only.

• Fully compliant with SD command/response sets and Physical Layer

as defined in the SD Memory Card Specifications, v3.0 including

high-capacity SDHC cards up to 32 GB and SDXC cards up to 2TB.

• Fully compliant with SDIO command/response sets and

interrupt/read-wait mode as defined in the SDIO Card Specification,

Part E1, v1.10

• Fully compliant with SD Card Specification, Part A2, SD Host

Controller Standard Specification, v2.00

All four ports support:

• 1-bit or 4-bit transfer mode specifications for SD and SDIO cards up to

UHS-I SDR104 mode (104 MB/s max)

• 1-bit, 4-bit, or 8-bit transfer mode specifications for MMC cards up to 52

MHz in both SDR and DDR modes (104 MB/s max)

However, the SoC-level integration and I/O muxing logic restrict the

functionality to the following:

• Instances #1 and #2 are primarily intended to serve as external slots or

interfaces to on-board SDIO devices. These ports are equipped with

“Card Detection” and “Write Protection” pads and do not support

hardware reset.

• Instances #3 and #4 are primarily intended to serve interfaces to

embedded MMC memory or interfaces to on-board SDIO devices.

These ports do not have “Card detection” and “Write Protection” pads

and do support hardware reset.

• All ports can work with 1.8 V and 3.3 V cards. There are two completely

independent I/O power domains for Ports #1 and #2 in four bit

configuration (SD interface). Port #3 is placed in his own independent

power domain and port #4 shares power domain with some other

interfaces.

VDOA VDOA Multimedia

Peripherals

The Video Data Order Adapter (VDOA) is used to re-order video data from

the “tiled” order used by the VPU to the conventional raster-scan order

needed by the IPU.

VPU Video Processing

Unit

Multimedia

Peripherals

A high-performing video processing unit (VPU), which covers many

SD-level and HD-level video decoders and SD-level encoders as a

multi-standard video codec engine as well as several important video

processing, such as rotation and mirroring.

See the i.MX 6Dual/6Quad reference manual (IMX6DQRM) for complete

list of VPU’s decoding/encoding capabilities.

WDOG-1 Watchdog Timer

Peripherals

The Watchdog Timer supports two comparison points during each

counting period. Each of the comparison points is configurable to evoke

an interrupt to the Arm core, and a second point evokes an external event

on the WDOG line.

Table 2. i.MX 6Dual/6Quad Modules List (continued)

Block

Mnemonic

Block Name Subsystem Brief Description

Modules List

i.MX 6Dual/6Quad Applications Processors for Consumer Products, Rev. 6, 11/2018

NXP Semiconductors 19

3.1 Special Signal Considerations

The package contact assignments can be found in Section 6, “Package Information and Contact

Assignments.” Signal descriptions are defined in the i.MX 6Dual/6Quad reference manual (IMX6DQRM).

Special signal consideration information is contained in the Hardware Development Guide for i.MX

6Quad, 6Dual, 6DualLite, 6Solo Families of Applications Processors (IMX6DQ6SDLHDG).

3.2 Recommended Connections for Unused Analog Interfaces

The recommended connections for unused analog interfaces can be found in the section, “Unused analog

interfaces,” of the Hardware Development Guide for i.MX 6Quad, 6Dual, 6DualLite, 6Solo Families of

Applications Processors (IMX6DQ6SDLHDG).

WDOG-2

(TZ)

Watchdog

(TrustZone)

Timer

Peripherals

The TrustZone Watchdog (TZ WDOG) timer module protects against

TrustZone starvation by providing a method of escaping normal mode and

forcing a switch to the TZ mode. TZ starvation is a situation where the

normal OS prevents switching to the TZ mode. Such a situation is

undesirable as it can compromise the system’s security. Once the TZ

WDOG module is activated, it must be serviced by TZ software on a

periodic basis. If servicing does not take place, the timer times out. Upon

a time-out, the TZ WDOG asserts a TZ mapped interrupt that forces

switching to the TZ mode. If it is still not served, the TZ WDOG asserts a

security violation signal to the CSU. The TZ WDOG module cannot be

programmed or deactivated by a normal mode Software.

EIM NOR-Flash /PSRAM

interface

Connectivity

Peripherals

The EIM NOR-FLASH / PSRAM provides:

• Support 16-bit (in muxed IO mode only) PSRAM memories (sync and

async operating modes), at slow frequency

• Support 16-bit (in muxed IO mode only) NOR-Flash memories, at slow

frequency

• Multiple chip selects

XTALOSC Crystal Oscillator

interface

— The XTALOSC module enables connectivity to external crystal oscillator

device. In a typical application use-case, it is used for 24 MHz oscillator.

Table 2. i.MX 6Dual/6Quad Modules List (continued)

Block

Mnemonic

Block Name Subsystem Brief Description

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i.MX 6Dual/6Quad：高性能低功耗多媒体应用处理器

i.MX6Dual6Quad数据手册

i.MX 6Dual/6Quad Applications Processor Reference Manual

freescale i.MX 6Dual6Quad 芯片手册

makefile hdl_fl_para += -f ../../../hdl/$(project)/file_list/mx2_core_rtl_for_netlist_file_list.f

Freescale i.MX6ULL开发板视频监控系统 和 i.MX6ULL视频监控系统的最新开源地址

链接https://www.ibm.com/support/knowledgecenter/SSYMRC_6.0.6/com.ibm.team.build.doc/topics/t_scal_build_resrc.html失效，请提供新的有效链接

这条命令是什么意思：kubectl set image deployments/common-uat uat-common=registry.cn-hangzhou.aliyuncs.com/mx_586/common_uat:$DID

i.mx6u yocto 构建根文件系统

i i .mx6u 嵌入式 l lx inux 驱动 开发指南

i.mx6ull pcb

下载imx6ull数据手册的网站

gdown https://mirrors.huaweicloud.com/chromedriver/uc?id=1MX3ZCnwqyRztG1vFRiHkKTz68ZJeHS4Y

i.mx6u datasheet

初始化i.mx6ull iic通信

i.mx6ull linux security

i.mx6u spl uboot

STM32MP157和I.MX6ULL的区别

I.MX6U-ALPHA开发板的介绍

kubectl set image deployments/common-uat uat-common=registry.cn-hangzhou.aliyuncs.com/mx_586/common_uat:$DID这条命令会更新pod，但是会先删除旧pod，怎么能让他先完全启动后才删除旧pod

最新资源

Freescale i.MX6ULL开发板视频监控系统和 i.MX6ULL视频监控系统的最新开源地址

i i .mx6u 嵌入式 l lx inux 驱动开发指南