三星S3C4510B：集成以太网控制器的RISC微控制器

s3c4510B

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"s3c4510B是一款由三星公司推出的16/32位RISC微控制器，主要用于基于以太网的系统，尤其适用于管理型通信集线器和路由器。这款微控制器以高性能、低功耗的ARM7TDMI RISC处理器为核心，提供了集成的以太网控制器，降低了系统的总体成本。它还配备了一个可配置的8K字节统一缓存/SRAM和以太网控制器，进一步优化了性能和成本。此外，S3C4510B还包括两个HDLC通道、两个UART通道和多个其他外围功能，如定时器等。该芯片采用HDL综合器设计，并在三星的先进ASIC测试环境中进行全面验证。" 详细说明： 1. **产品概述**：S3C4510B是三星推出的一款高性价比、高性能的16/32位RISC微控制器，专为基于以太网的系统而设计。其核心功能在于集成的以太网控制器，使得该芯片在管理型通信设备如集线器和路由器中表现出色。 2. **处理器核心**：S3C4510B采用ARM7TDMI（Thumb Data Manipulation Instruction Set）RISC处理器，由Advanced RISC Machines Ltd设计。ARM7TDMI是一种低功耗、通用目的的微处理器，适用于特定应用和定制集成电路。其简单、优雅且完全静态的设计，特别适合对成本和功耗敏感的应用。 3. **缓存与内存**：该微控制器提供了一个可配置的8K字节统一缓存/SRAM，这在提高数据访问速度的同时，减少了对外部存储器的需求，降低了系统的整体成本。 4. **以太网控制器**：集成的以太网控制器是S3C4510B的关键特性之一，增强了其在以太网通信中的功能，简化了系统设计，减少了外部组件。 5. **外围接口**：S3C4510B还包含多种外围接口，如两个HDLC（高级数据链路控制）通道，支持数据通信，每个都带有缓冲描述符；两个UART（通用异步收发传输器）通道，用于串行通信；以及其它未在描述中明确列出但通常在微控制器中常见的功能，例如定时器、中断控制器等。 6. **设计与验证**：大部分片上功能块使用HDL（硬件描述语言）合成技术进行设计，确保了高度的灵活性和优化。S3C4510B在三星的高级ASIC（应用特定集成电路）测试环境中进行了全面验证，确保了芯片的可靠性和性能。 S3C4510B微控制器是为满足以太网通信需求而设计的高效解决方案，它的强大功能、低功耗特性和集成的特性使其在嵌入式系统设计中具有很高的价值。

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PRODUCT OVERVIEW S3C4510B

1-16

Table 1-3. S3C4510B PAD Type

Pad Type I/O Type Current

Drive

Cell Type Feature Slew-Rate

Control

ptic I – LVCMOS level 5 V-tolerant –

ptis I – LVCMOS schmit trigger level 5 V-tolerant –

pticu I – LVCMOS level 5 V-tolerant

Pull-up register

–

pticd I – LVCMOS level 5 V-tolerant

Pull-down register

–

pia_bb I – Analog input with seperate bulk bias – –

pob1 O 1 mA Normal buffer – –

ptot2 O 2 mA Tri-state buffer 5 V-tolerant –

pob4 O 4 mA Normal buffer – –

ptot4 O 4 mA Tri-state buffer 5 V-tolerant –

ptot6 O 6 mA Tri-state buffer 5 V-tolerant –

ptbsut1 I/O 1 mA LVCMOS schmit trigger level

Tri-state buffer

5 V-tolerant

Pull-up register

–

ptbcut4 I/O 4 mA LVCMOS level Tri-state buffer 5 V-tolerant Medium

ptbcd4 I/O 4 mA LVCMOS level open drain buffer 5 V-tolerant –

ptbst4sm I/O 4 mA LVCMOS schmit trigger level 5 V-tolerant Medium

Ptbsut6 I/O 6 mA LVCMOS schmit trigger level 5 V-tolerant

Pull-up register

–

NOTE: pticu and pticd provides 100K Ohm Pull-up(down) register. For detail information about the pad type, see Chapter 4.

Input/Output Cells of the "STD90/MDL90 0.35 um 3.3 V Standard Cell Library Data Book", produced by Samsung

Electrionic Co., Ltd, ASIC Team.

64*f

MCLK

512*f

MCLK

nRESET

nRSCO

NOTE: After the falling edge of nRESET, the S3C4510B count 64 cycles for a system reset

and needs further 512 cycles for a TAG RAM clear of cache.

After these cycles, the S3C4510B asserts nRCS0 when the nRESET is released.

Figure 1-3. Reset Timing Diagram

S3C4510B PRODUCT OVERVIEW

1-17

CPU CORE OVERVIEW

The S3C4510B CPU core is a general purpose 32-bit ARM7TDMI microprocessor, developed by Advanced RISC

Machines, Ltd. (ARM). The core architecture is based on Reduced Instruction Set Computer (RISC) principles.

The RISC architecture makes the instruction set and its related decoding mechanism simpler and more efficient

than those with microprogrammed Complex Instruction Set Computer (CISC) systems. High instruction

throughput and impressive real-time interrupt response are among the major beneifts of the architecture.

Pipelining is also employed so that all components of the processing and memory systems can operate

continuously. The ARM7TDMI has a 32-bit address bus.

An important feature of the ARM7TDMI processor that makes itself distinct from the ARM7 processor is a unique

architectural strategy called THUMB. The THUMB strategy is an extension of the basic ARM architecture

consisting of 36 instruction formats. These formats are based on the standard 32-bit ARM instruction set, while

having been re-coded using 16-bit wide opcodes.

As THUMB instructions are one-half the bit width of normal ARM instructions, they produce very high-density

codes. When a THUMB instruction is executed, its 16-bit opcode is decoded by the processor into its equivalent

instruction in the standard ARM instruction set. The ARM core then processes the 16-bit instruction as it would a

normal 32-bit instruction. In other words, the THUMB architecture gives 16-bit systems a way to access the 32-bit

performance of the ARM core without requiring the full overhead of 32-bit processing.

As the ARM7TDMI core can execute both standard 32-bit ARM instructions and 16-bit THUMB instructions, it

allows you to mix the routines of THUMB instructions and ARM code in the same address space. In this way, you

can adjust code size and performance, routine by routine, to find the best programming solution for a specific

application.

Address

Incrementer

Multiplier

Barrel

Shifter

32-Bit ALU

Write Data

Instruction

Decoder and

Logic Controll

Instruction

Pipeline and Read

Data Register

Figure 1-4. ARM7TDMI Core Block Diagram

PRODUCT OVERVIEW S3C4510B

1-18

INSTRUCTION SET

The S3C4510B instruction set is divided into two subsets: a standard 32-bit ARM instruction set and a 16-bit

THUMB instruction set.

The 32-bit ARM instruction set is comprised of thirteen basic instruction types, which can, in turn, be divided into

four broad classes:

• Four types of branch instructions which control program execution flow, instruction privilege levels, and

switching between an ARM code and a THUMB code.

• Three types of data processing instructions which use the on-chip ALU, barrel shifter, and multiplier to

perform high-speed data operations in a bank of 31 registers (all with 32-bit register widths).

• Three types of load and store instructions which control data transfer between memory locations and the

registers. One type is optimized for flexible addressing, another for rapid context switching, and the third for

swapping data.

• Three types of co-processor instructions which are dedicated to controlling external co-processors. These

instructions extend the off-chip functionality of the instruction set in an open and uniform way.

NOTE

All 32-bit ARM instructions can be executed conditionally.

The 16-bit THUMB instruction set contains 36 instruction formats drawn from the standard 32-bit ARM instruction

set. The THUMB instructions can be divided into four functional groups:

• Four branch instructions.

• Twelve data processing instructions, which are a subset of the standard ARM data processing instructions.

• Eight load and store register instructions.

• Four load and store multiple instructions.

NOTE

Each 16-bit THUMB instruction has a corresponding 32-bit ARM instruction with an identical

processing model.

The 32-bit ARM instruction set and the 16-bit THUMB instruction set are good targets for compilers of many

different high-level languages. When an assembly code is required for critical code segments, the ARM

programming technique is straightforward, unlike that of some RISC processors which depend on sophisticated

compiler technology to manage complicated instruction interdependencies.

Pipelining is employed so that all parts of the processor and memory systems can operate continuously.

Typically, while one instruction is being executed, its successor is being decoded, and the third instruction is

being fetched from memory.

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三星S3C4510B：集成以太网控制器的RISC微控制器

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module First_M(A,B,Ci,F,Co); input A,B,Ci; output F,Co; wire A,B,Ci,F,Co; wire S1,S2,S3; xor XU1(F,A,B,Ci), XU2(S1,A,B); and AU1(S2,A,B), AU2(S3,S1,Ci); or OU1(Co,S2,S3); endmodule解释每一行代码的意思

module First_M(A,B,Ci,F,Co); input A,B,Ci; output F,Co; wire A,B,Ci,F,Co; wire S1,S2,S3; xor XU1(F,A,B,Ci), XU2(S1,A,B); and AU1(S2,A,B), AU2(S3,S1,Ci); or OU1(Co,S2,S3); endmodule module test;每行代码的意思是什么

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Verilog代码：module First_M(A,B,Ci,F,Co); input A,B,Ci; //三个输入 output F,Co; //两个输出 wire A,B,Ci,F,Co; wire S1,S2,S3; xor XU1(F,A,B,Ci), XU2(S1,A,B); and AU1(S2,A,B), AU2(S3,S1,Ci); or OU1(Co,S2,S3); endmodule，加注释

假如有以下程序段。S1+:a=5-x;+S2+:b=3*a;+S3:c=a+b;+S4+:d=b+2;+(1)试画图表示它们执行时的先后次序。(2)利用Bernstein条件证明+

module First_M(A,B,Ci,F,Co); input A,B,Ci; output F,Co; wire A,B,Ci,F,Co; wire S1,S2,S3; xor XU1(F,A,B,Ci), XU2(S1,A,B); and AU1(S2,A,B), AU2(S3,S1,Ci); or OU1(Co,S2,S3); endmodule每一行代码的意思

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