Verilog黄金参考手册：快速掌握硬件描述语言

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《Verilog黄金指南》是由Doulos公司编写的权威参考资料，专为理解和掌握Verilog硬件描述语言而设计。Verilog是一种广泛应用于电子设计自动化（EDA）领域的高级硬件描述语言，由Cadence Design Systems Inc.所有并注册商标。该指南并非IEEE标准Verilog语言参考手册的全面替代，而是旨在提供一个简洁、快速的参考工具，帮助用户了解Verilog的语法、语义、综合方法以及在硬件设计中的实际应用。该指南的核心内容包括： 1. **Verilog语言简介**：介绍Verilog的基本概念，它是一种用于描述数字电路行为的语言，通过文本形式表达系统级的硬件结构和功能。 2. **语法概览**：涵盖了Verilog的关键组成部分，如模块定义、数据类型、信号声明、过程（如函数和任务）、组合逻辑、顺序逻辑等，以及如何正确编写可读性强且易于理解的代码。 3. **语义与行为描述**：讲解了Verilog如何描述信号的行为，包括时序逻辑、事件驱动与非事件驱动的流程控制，以及模块间的接口和交互。 4. **综合与仿真**：指南详细解释了如何将Verilog设计输入到综合工具中，使之转化为门级或网表形式，同时介绍了仿真环境，如波形分析和逻辑验证的重要性。 5. **最佳实践与应用示例**：为了帮助读者更好地理解和应用Verilog，书中提供了实用的技巧和案例研究，展示了如何在实际设计中优化代码，提高设计效率。 6. **限制与注意事项**：指南还强调了Verilog的一些潜在限制和可能遇到的问题，以及如何避免常见错误，确保设计的正确性和有效性。《Verilog黄金指南》作为一本实用参考工具，适用于Verilog初学者和经验丰富的设计师，无论是学习Verilog基础，还是在项目中快速查阅特定问题的答案，都能提供极大的便利。由于版权和使用限制，必须获得Doulos的书面许可才能复制或传播其内容。版本1.0发布于1996年8月，反映了当时的Verilog语言版本和行业实践。

A statement which conditionally executes at most one branch, depending on

the value of the case expression.

Syntax

CaseKeyword

(

Expression

)

Expression,...

Statement

{Expression may be variable}

Expression,...

Statement

... {Any number of cases}

[default [:]

Statement

] {Need not be at the end}

endcase

CaseKeyword =

{either} case casex casez

Where

See Statement.

Rules

Xs and Zs in a casex statement, and Zs in a casez statement mean “don’t

care”.

One default statement at most may be included. It is executed if no label

expressions match the case expression. (A ‘label’ is an expression or a

comma-separated list of expressions on the left of a colon, or the reserved

word default, which may or may not be followed by a colon.)

Where a label is a comma-separated list of two or more expressions, the label

is matched if the case expression matches any one of the label expressions.

If no label expressions match the case expression and there is no default

statement, the case statement has no effect.

Gotchas!

If more than one statement is to be executed for a particular label, the

statements must be enclosed in a begin-end or fork-join block.

A branch is only executed if the corresponding label is the first one to match

the case expression. Case labels need not be mutually exclusive, so a

Verilog compiler will not report an error where the same label has erroneously

been repeated.

The syntax of a casex or casez statement ends with the reserved word

endcase, not endcasex or endcasez.

An X or Z in the casex expression or a Z in a casez expression is matched

with any value in a case label. This may give confusing simulation results.

Synthesis

Assignments within case statements generally synthesize to multiplexers. If

variables (i.e. registers or nets) are used for case labels, priority encoders

may be synthesized.

Case

Coding standards are divided into two categories. Lexical coding standards,

which control text layout, naming conventions and commenting, are intended

to improve readability and ease of maintenance. Synthesis coding standards,

which control Verilog style, are intended to avoid common synthesis pitfalls

and find synthesis errors early in the design flow.

The following lists of coding standards will need to be modified according to

the choice of tools and personal preferences.

Lexical Coding Standards

Limit the contents of each Verilog source file to one module, and do not split

modules across files.

Source file names should relate to the file contents (e.g. ModuleName.v).

Write only one declaration or statement per line.

Use indentation as shown in the examples.

Be consistent about the case of user defined names (e.g. first letter a capital).

User defined names should be meaningful and informative, although local

names (e.g. loop variables) may be terse.

Write comments to explain (not duplicate) the Verilog code. It is particularly

important to comment interfaces (e.g. module parameters, ports, task and

function arguments).

Use parameters or `define macros wherever possible, instead of directly

embedding literal numbers and strings in declarations and statements.

Synthesis Coding Standards

Partition the design into small functional blocks, and use a behavioural style

for each block. Avoid gate level descriptions except for critical parts of the

design.

Have a well defined clocking strategy, and implement that strategy explicitly in

Verilog (e.g. single clock, multi-phase clocks, gated clocks, multiple clock

domains). Ensure that clock and reset signals in Verilog are clean (i.e. not

generated from combinational logic or unintentionally gated).

Have a well defined (manufacturing) testing strategy, and code up the Verilog

appropriately (e.g. all flipflops resettable, test access from external pins, no

functional redundancy).

Every Verilog always should conform to one of the standard synthesizable

process templates (see

Always

An always describing combinational and latched logic must have all of the

inputs in the event control list at the top of the always.

A combinational always must not contain incomplete assignments, i.e. all

outputs must be assigned for all combinations of input values.

An always describing combinational and latched logic must not contain

feedback, i.e. registers assigned as outputs from the always must not be

read as inputs to the always.

Coding Standards

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