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Exynos 4412 SCP 用户手册_v0.10.00 初步指南
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更新于2024-07-15
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"SEC_Exynos 4412 SCP_Users Manual_Ver.0.10.00_Preliminary"
Exynos 4412 是三星(Samsung Electronics Co., Ltd.)推出的一款高性能的系统级芯片(System-on-Chip, SOC),主要应用于智能手机和平板电脑等移动设备。SCP(System Control Processor)是该芯片中一个重要的微处理器组件,负责管理系统的整体控制和电源管理。本用户手册详细介绍了Exynos 4412 SCP的使用和配置,供开发人员和工程师参考。
手册中的RISC(Reduced Instruction Set Computer)指的是SCP使用的微处理器架构,这是一种精简指令集,旨在提高执行效率和降低功耗。Exynos 4412 SCP基于RISC架构,可能是为了在保持高效性能的同时,满足移动设备对低功耗的需求。
版本号0.10.00表明这是该手册的一个初步版本,可能会有后续更新以反映产品的新特性和改进。手册发布日期为2012年4月,由Samsung Electronics Co., Ltd.所有,并在2012年5月7日进行了最后一次编辑。
文档包含了重要的注意事项,三星保留随时修改此出版物信息的权利,且不承担因使用其中信息可能产生的任何错误、遗漏或后果的责任。此外,手册本身并不授予任何关于三星或第三方产品的知识产权许可,使用者需自行确保遵循相关知识产权法律。
三星明确声明,其产品不保证适用于特定目的,并且对于使用任何产品或电路引起的任何责任,包括但不限于间接或附带损害,三星均不承担责任。这表明用户在使用Exynos 4412 SCP时需要自行评估风险,并理解可能存在的技术限制和潜在问题。
总体来说,这个用户手册是Exynos 4412 SCP的开发者和设计者的重要参考资料,它提供了关于如何有效利用和配置SCP以实现最佳系统性能和电源管理的详细指南。手册内容可能涵盖SCP的硬件接口、软件编程模型、电源管理策略以及故障排查等内容,帮助工程师理解和优化基于Exynos 4412平台的设备。
35.8 IO Description .................................................................................................................................... 35-19
35.9 Register Description ........................................................................................................................... 35-20
35.9.1 Register Map Summary .............................................................................................................. 35-20
36 IIS-BUS INTERFACE ................................................................................. 36-1
36.1 Overview .............................................................................................................................................. 36-1
36.2 Features ............................................................................................................................................... 36-1
36.3 Block Diagram ...................................................................................................................................... 36-2
36.4 Functional Description ......................................................................................................................... 36-3
36.4.1 Master/Slave Mode ....................................................................................................................... 36-3
36.4.2 DMA Transfer ............................................................................................................................... 36-4
36.4.3 Audio Serial Data Format ............................................................................................................. 36-5
36.4.4 PCM Word Length and BFS Divider ............................................................................................. 36-8
36.4.5 BFS Divider and RFS Divider ....................................................................................................... 36-8
36.4.6 RFS Divider and Root Clock ......................................................................................................... 36-8
36.5 Programming Guide ............................................................................................................................. 36-9
36.5.1 Initialization ................................................................................................................................... 36-9
36.5.2 Play Mode (Tx Mode) with DMA ................................................................................................... 36-9
36.5.3 Recording Mode (Rx Mode) with DMA ......................................................................................... 36-9
36.5.4 Example Code ............................................................................................................................ 36-10
36.6 I/O Description ................................................................................................................................... 36-16
36.7 Register Description ........................................................................................................................... 36-17
36.7.1 Register Map Summary .............................................................................................................. 36-17
37 AC97 CONTROLLER ................................................................................ 37-1
37.1 Overview .............................................................................................................................................. 37-1
37.2 Features ............................................................................................................................................... 37-1
37.3 AC97 Controller Operation ................................................................................................................... 37-2
37.3.1 Block Diagram .............................................................................................................................. 37-2
37.3.2 Internal Data Path ......................................................................................................................... 37-3
37.3.3 Operation Flow Chart ................................................................................................................... 37-4
37.3.4 AC-link Digital Interface Protocol .................................................................................................. 37-5
37.3.5 AC-link Input Frame (SDATA_IN) ................................................................................................. 37-7
37.3.6 AC97 Power-Down ....................................................................................................................... 37-9
37.4 I/O Description ................................................................................................................................... 37-12
37.5 Register Description ........................................................................................................................... 37-13
37.5.1 Register Map Summary .............................................................................................................. 37-13
38 PCM AUDIO INTERFACE ......................................................................... 38-1
38.1 Overview .............................................................................................................................................. 38-1
38.2 Features ............................................................................................................................................... 38-1
38.3 PCM Audio Interface ............................................................................................................................ 38-2
38.4 PCM Timing ......................................................................................................................................... 38-3
38.5 I/O Description ..................................................................................................................................... 38-5
38.6 Register Description ............................................................................................................................. 38-6
38.6.1 Register Map Summary ................................................................................................................ 38-6
39 SPDIF TRANSMITTER .............................................................................. 39-1
39.1 Overview .............................................................................................................................................. 39-1
39.2 Features ............................................................................................................................................... 39-1
39.3 Block Diagram ...................................................................................................................................... 39-2
samsung / david.pang at 14:21,2012.05.07
SAMSUNG Confidential
39.4 Functional Description ......................................................................................................................... 39-3
39.4.1 Data Format of SPDIF .................................................................................................................. 39-3
39.4.2 Channel Coding ............................................................................................................................ 39-6
39.4.3 Preamble ...................................................................................................................................... 39-6
39.4.4 Non-Linear PCM-Encoded Source (IEC 61937) .......................................................................... 39-7
39.4.5 SPDIF Operation .......................................................................................................................... 39-9
39.4.6 Shadowed Register .................................................................................................................... 39-10
39.5 I/O Description ................................................................................................................................... 39-11
39.6 Register Description ........................................................................................................................... 39-12
39.6.1 Register Map Summary .............................................................................................................. 39-12
40 HIGH-SPEED SYNCHRONOUS SERIAL INTERFACE (HSI) ................... 40-1
40.1 Overview .............................................................................................................................................. 40-1
40.2 Features ............................................................................................................................................... 40-1
40.3 Functional Description ......................................................................................................................... 40-2
40.3.1 Block Diagram .............................................................................................................................. 40-2
40.3.2 Interface Port Description ............................................................................................................. 40-4
40.3.3 Programming Basic Sequence Guide .......................................................................................... 40-5
40.4 Register Description ........................................................................................................................... 40-11
40.4.1 Register Map Summary .............................................................................................................. 40-11
41 DISPLAY CONTROLLER .......................................................................... 41-1
41.1 Overview .............................................................................................................................................. 41-1
41.2 Features of Display Controller ............................................................................................................. 41-2
41.3 Functional Description ......................................................................................................................... 41-4
41.3.1 Brief Description of the Sub-Block ................................................................................................ 41-4
41.3.2 Data Flow ...................................................................................................................................... 41-5
41.3.3 Overview of the Color Data .......................................................................................................... 41-8
41.3.4 Color Space Conversion ............................................................................................................. 41-23
41.3.5 Palette Usage ............................................................................................................................. 41-25
41.3.6 Window Blending ........................................................................................................................ 41-28
41.3.7 Image Enhancement .................................................................................................................. 41-37
41.3.8 VTIME Controller Operation ....................................................................................................... 41-44
41.3.9 Setting of Commands ................................................................................................................. 41-47
41.3.10 Virtual Display ........................................................................................................................... 41-50
41.3.11 RGB Interface Specification ..................................................................................................... 41-51
41.3.12 LCD Indirect i80 System Interface ............................................................................................ 41-60
41.4 I/O Description ................................................................................................................................... 41-64
41.5 Register Description ........................................................................................................................... 41-65
41.5.1 Register Map Summary .............................................................................................................. 41-66
41.5.2 Palette Memory ........................................................................................................................... 41-72
41.5.3 Control Register .......................................................................................................................... 41-73
41.5.4 Gamma Lookup Table .............................................................................................................. 41-145
41.5.5 Shadow Windows Control ........................................................................................................ 41-146
41.5.6 Palette Ram .............................................................................................................................. 41-147
42 CAMERA INTERFACE AND SCALER ...................................................... 42-1
42.1 Overview .............................................................................................................................................. 42-1
42.2 Features of CAMIF ............................................................................................................................... 42-3
42.3 External Interface ................................................................................................................................. 42-5
42.4 Timing Diagram and Data Alignment of Camera ................................................................................. 42-6
samsung / david.pang at 14:21,2012.05.07
SAMSUNG Confidential
42.4.1 Timing Diagram of ITU Camera .................................................................................................... 42-6
42.4.2 MIPI CSI Data Alignment from MIPI Camera ............................................................................. 42-10
42.5 External Connection Guide ................................................................................................................ 42-11
42.6 Camera Interface Operation .............................................................................................................. 42-12
42.6.1 Input/Output DMA Ports ............................................................................................................. 42-12
42.6.2 Clock Domain ............................................................................................................................. 42-13
42.6.3 Frame Memory Hierarchy ........................................................................................................... 42-14
42.6.4 Memory Storing Method ............................................................................................................. 42-15
42.6.5 Timing Diagram for Register Setting .......................................................................................... 42-16
42.6.6 Timing Diagram for last IRQ ....................................................................................................... 42-18
42.6.7 Timing Diagram for IRQ (Memory Data Scaling Mode).............................................................. 42-20
42.6.8 Input DMA Feature ..................................................................................................................... 42-21
42.6.9 Camera Interlace Input Support ................................................................................................. 42-22
42.7 Input/Output Description .................................................................................................................... 42-23
42.8 Register Description ........................................................................................................................... 42-24
42.8.1 Register Map Summary .............................................................................................................. 42-24
43 FIMC_LITE (CAMERA INTERFACE) ........................................................ 43-1
43.1 Overview of Camera Interface in FIMC_LITE ...................................................................................... 43-1
43.1.1 Block Diagram .............................................................................................................................. 43-1
43.2 Timing Diagram and Data Alignment of Camera ................................................................................. 43-2
43.2.1 Parallel INTERFACE .................................................................................................................... 43-2
43.2.2 MIPI CSI Slave Interface .............................................................................................................. 43-3
43.2.3 Local Output Interface Data Alignment ........................................................................................ 43-4
43.3 External Connection Guide .................................................................................................................. 43-5
43.4 Input / Output Path ............................................................................................................................... 43-6
43.5 I/O Description ..................................................................................................................................... 43-7
43.6 Register Description ............................................................................................................................. 43-8
43.6.1 Register Map ................................................................................................................................ 43-8
44 MIPI-DSI MASTER .................................................................................... 44-1
44.1 Overview .............................................................................................................................................. 44-1
44.2 Features ............................................................................................................................................... 44-1
44.2.1 Block Diagram .............................................................................................................................. 44-2
44.2.2 Interfaces and Protocol ................................................................................................................. 44-6
44.2.3 Configuration .............................................................................................................................. 44-16
44.2.4 Dual Display versus Single Display ............................................................................................ 44-17
44.2.5 PLL ............................................................................................................................................. 44-18
44.2.6 Buffer .......................................................................................................................................... 44-18
44.3 I/O Description ................................................................................................................................... 44-19
44.4 Register Description ........................................................................................................................... 44-20
44.4.1 Register Map Summary .............................................................................................................. 44-20
44.5 DPHY PLL Control ............................................................................................................................. 44-39
44.5.1 PMS Setting Sample for MIPI PLL ............................................................................................. 44-39
45 MIPI-CSI SLAVE (MIPI-CSI) ...................................................................... 45-1
45.1 Overview of MIPI CSIS ........................................................................................................................ 45-1
45.2 Features ............................................................................................................................................... 45-1
45.3 Block Diagram ...................................................................................................................................... 45-2
45.4 Interface and Protocol .......................................................................................................................... 45-3
45.5 Data Format ......................................................................................................................................... 45-4
samsung / david.pang at 14:21,2012.05.07
SAMSUNG Confidential
45.5.1 Data Alignment ............................................................................................................................. 45-4
45.5.2 YUV422 8-bit Order ...................................................................................................................... 45-4
45.6 I/O Description ..................................................................................................................................... 45-5
45.7 Register Description ............................................................................................................................. 45-6
45.7.1 Register Map Summary ................................................................................................................ 45-6
46 2D GRAPHIC ACCELERATOR ................................................................. 46-1
46.1 Overview .............................................................................................................................................. 46-1
46.2 Features ............................................................................................................................................... 46-2
46.2.1 Host Interface ............................................................................................................................... 46-2
46.2.2 Primitives ...................................................................................................................................... 46-2
46.2.3 Per-pixel Operation ....................................................................................................................... 46-3
46.2.4 Data Format .................................................................................................................................. 46-3
46.3 Host Interface: DMA Mode ................................................................................................................... 46-4
46.4 Color Format Conversion ..................................................................................................................... 46-9
46.4.1 RGBA Format ............................................................................................................................... 46-9
46.5 Rendering Pipeline ............................................................................................................................. 46-11
46.5.1 Primitive Drawing ........................................................................................................................ 46-12
46.5.2 Rotation and Addressing Direction (Flip) .................................................................................... 46-15
46.5.3 Clipping ....................................................................................................................................... 46-17
46.5.4 Color Key .................................................................................................................................... 46-18
46.5.5 Raster Operation ........................................................................................................................ 46-19
46.5.6 Mask Operation .......................................................................................................................... 46-21
46.5.7 Alpha Blending............................................................................................................................ 46-22
46.5.8 Fast Solid Color Fill..................................................................................................................... 46-26
46.6 Register Description ........................................................................................................................... 46-27
46.6.1 Register Map Summary .............................................................................................................. 46-27
46.6.2 General Registers ....................................................................................................................... 46-31
46.6.3 Command Registers ................................................................................................................... 46-37
46.6.4 Parameter Setting Registers ...................................................................................................... 46-43
46.6.5 Source ........................................................................................................................................ 46-45
46.6.6 Destination .................................................................................................................................. 46-50
46.6.7 Pattern ........................................................................................................................................ 46-54
46.6.8 Mask ........................................................................................................................................... 46-56
46.6.9 Clipping Window ......................................................................................................................... 46-60
46.6.10 ROP & Alpha Setting ................................................................................................................ 46-62
46.6.11 Color ......................................................................................................................................... 46-63
46.6.12 Color Key .................................................................................................................................. 46-65
46.6.13 Gamma Table ........................................................................................................................... 46-68
47 3D GRAPHIC ACCELERATOR (G3D) ...................................................... 47-1
47.1 Overview of G3D .................................................................................................................................. 47-1
47.2 Features of G3D................................................................................................................................... 47-2
47.3 Architecture Brief of G3D ..................................................................................................................... 47-3
47.4 G3D Structure ...................................................................................................................................... 47-4
47.5 GPU Hardware Architecture ................................................................................................................ 47-5
47.5.1 Top-level System .......................................................................................................................... 47-5
47.5.2 Functional Block Diagram of GPU Hardware Architecture ........................................................... 47-6
47.5.3 PMU Hardware Architecture ......................................................................................................... 47-8
47.5.4 Level 2 Cache Controller Hardware Architecture ......................................................................... 47-9
48 IMAGE ROTATOR ..................................................................................... 48-1
samsung / david.pang at 14:21,2012.05.07
SAMSUNG Confidential
48.1 Overview of Image Rotator .................................................................................................................. 48-1
48.2 Features of Image Rotator ................................................................................................................... 48-1
48.3 Block Diagram ...................................................................................................................................... 48-2
48.4 Supported Image Rotation Functions .................................................................................................. 48-3
48.5 Image Rotation with Windows Offset ................................................................................................... 48-4
48.6 Programming Guide ............................................................................................................................. 48-5
48.6.1 Resister Setting ............................................................................................................................ 48-5
48.6.2 Restrictions on the Image Size ..................................................................................................... 48-5
48.7 Register Description ............................................................................................................................. 48-6
48.7.1 Register Map Summary ................................................................................................................ 48-6
49 JPEG CODEC ............................................................................................ 49-1
49.1 Overview .............................................................................................................................................. 49-1
49.2 Features ............................................................................................................................................... 49-2
49.3 Color Component Data Ordering ......................................................................................................... 49-3
49.4 Register Description ............................................................................................................................. 49-4
49.4.1 Register Map Summary ................................................................................................................ 49-4
49.5 Programmer's Model .......................................................................................................................... 49-18
49.5.1 Encoder Flow Chart .................................................................................................................... 49-18
49.5.2 Programming QUAN_TBL_ENT and HUFF_TBL_ENT ............................................................. 49-19
49.6 Example Codes .................................................................................................................................. 49-21
49.7 References ......................................................................................................................................... 49-22
50 MULTI FORMAT CODEC (MFC) ............................................................... 50-1
50.1 Introduction .......................................................................................................................................... 50-1
50.1.1 Supported Standards .................................................................................................................... 50-1
50.1.2 Features ........................................................................................................................................ 50-3
50.1.3 Target Performance and Functions .............................................................................................. 50-4
50.2 Hardware Overview ............................................................................................................................. 50-6
50.2.1 Block Diagram .............................................................................................................................. 50-6
50.2.2 Frame Memory ............................................................................................................................. 50-8
50.3 Register Description ........................................................................................................................... 50-11
50.3.1 Register Map Summary .............................................................................................................. 50-11
50.3.2 Control Registers ........................................................................................................................ 50-19
50.3.3 Codec Registers ......................................................................................................................... 50-38
50.3.4 Encoding Registers .................................................................................................................... 50-59
50.4 Shared Memory Interface .................................................................................................................. 50-68
50.4.1 Host Interface ............................................................................................................................. 50-68
50.4.2 Shared Memory Structure .......................................................................................................... 50-69
50.5 Metadata Interface ............................................................................................................................. 50-87
50.5.1 Shared Memory Interface for Decoders ..................................................................................... 50-87
50.5.2 Shared Memory Interface for Encoders ..................................................................................... 50-91
50.6 Appendix ............................................................................................................................................ 50-92
50.6.1 Summary of Buffer Requirements .............................................................................................. 50-92
50.6.2 Batch Encoding Interface ........................................................................................................... 50-93
51 VIDEO PROCESSOR ................................................................................ 51-1
51.1 Overview of Video Processor ............................................................................................................... 51-1
51.1.1 Features ........................................................................................................................................ 51-1
51.2 Block Diagram ...................................................................................................................................... 51-2
51.3 Functional Description ......................................................................................................................... 51-3
samsung / david.pang at 14:21,2012.05.07
SAMSUNG Confidential
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