PCI Express 3.0 规范详解

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"PCI Express Base Specification Revision 3.0 是一个技术规格文档，该文档在2008年9月12日更新至版本0.5。它详细介绍了PCI Express协议的第三版，主要增加了5.0 GT/s的数据速率，并整合了批准的错误修复和工程变更通知（Errata and ECNs）。此规范由PCI-SIG组织进行会员审查，并强调不对此文档及其包含的信息提供任何保证或责任。用户需联系PCI-SIG获取最新修订版的规范。" PCI Express (PCIe) 协议是计算机系统中广泛使用的高速接口标准，用于连接各种设备，如显卡、网卡、硬盘等。PCIe 3.0是这个协议的一个重要版本，发布于2006年12月20日，随后在2008年9月12日进行了修订，更新至版本0.5。以下是对PCIe 3.0协议的关键知识点的详细说明： 1. **数据传输速率**：PCIe 3.0的最大数据传输速率为5.0 GT/s（Gigatransfers per second），比PCIe 2.0的2.5 GT/s翻了一倍。每个传输位（bit）可以携带两个数据位（lane），因此每个通道（lane）的带宽理论上限为1GB/s，4条lane的总带宽可达4GB/s（x4配置）。 2. **物理层（PHY）改进**：为了实现更高的数据速率，PCIe 3.0在物理层引入了更先进的信号处理技术，包括差分信号传输、回声抵消、均衡技术等，以降低信号噪声和提高信号完整性。 3. **低功耗设计**：PCIe 3.0引入了电源管理功能，如低功耗状态（L1.1和L1.2），允许设备在空闲时进入低功耗模式，从而减少整体系统能耗。 4. **错误检测与恢复机制**：协议中包含了错误检测和纠正机制，如前向纠错（Forward Error Correction, FEC），提高了数据传输的可靠性。 5. **链路协商**：PCIe 3.0继续保持链路协商功能，允许设备根据自身能力与主板上的插槽自动协商最佳的数据传输速率和lane数量。 6. **流量控制和数据包排序**：使用信用基流控制（Credit-Based Flow Control）和数据包重新排序机制，确保数据包的正确顺序到达接收端。 7. **多设备支持**：PCIe支持多设备并行连接，通过菊花链（daisy chaining）方式连接多个设备，允许系统扩展性和灵活性。 8. **兼容性**：尽管PCIe 3.0提升了性能，但依然向下兼容之前的PCIe 2.0和PCIe 1.1版本，确保了旧设备能够在新系统上正常工作。 9. **软件支持**：为了配合硬件规范，操作系统和驱动程序需要支持PCIe 3.0的特性，例如中断管理和资源分配等。 PCIe 3.0协议通过增加数据传输速率、优化信号质量、强化错误处理和节能设计，显著提升了系统间的通信效率和可靠性，为高性能计算和数据中心应用提供了强大的支持。在开发和设计基于PCIe 3.0的系统时，理解这些关键知识点至关重要。

PCI EXPRESS BASE SPECIFICATION, REV. 23.0, VER. 0.5

FIGURE 7-41: ERROR SOURCE IDENTIFICATION REGISTER .......................................................... 616

FIGURE 7-42: PCI EXPRESS VIRTUAL CHANNEL CAPABILITY STRUCTURE ................................. 618

FIGURE 7-43: VIRTUAL CHANNEL EXTENDED CAPABILITY HEADER .......................................... 619

IGURE 7-44: PORT VC CAPABILITY REGISTER 1 ....................................................................... 620

IGURE 7-45: PORT VC CAPABILITY REGISTER 2 ....................................................................... 621

FIGURE 7-46: PORT VC CONTROL REGISTER .............................................................................. 622

FIGURE 7-47: PORT VC STATUS REGISTER ................................................................................. 623

FIGURE 7-48: VC RESOURCE CAPABILITY REGISTER.................................................................. 624

IGURE 7-49: VC RESOURCE CONTROL REGISTER...................................................................... 626

IGURE 7-50: VC RESOURCE STATUS REGISTER......................................................................... 628

FIGURE 7-51: EXAMPLE VC ARBITRATION TABLE WITH 32 PHASES........................................... 630

FIGURE 7-52: EXAMPLE PORT ARBITRATION TABLE WITH 128 PHASES AND 2-BIT TABLE ENTRIES

............................................................................................................................................. 631

IGURE 7-53: PCI EXPRESS DEVICE SERIAL NUMBER CAPABILITY STRUCTURE......................... 632

IGURE 7-54: DEVICE SERIAL NUMBER EXTENDED CAPABILITY HEADER.................................. 633

FIGURE 7-55: SERIAL NUMBER REGISTER................................................................................... 634

FIGURE 7-56: PCI EXPRESS ROOT COMPLEX LINK DECLARATION CAPABILITY ......................... 636

FIGURE 7-57: ROOT COMPLEX LINK DECLARATION EXTENDED CAPABILITY HEADER............... 636

FIGURE 7-58: ELEMENT SELF DESCRIPTION REGISTER ............................................................... 637

FIGURE 7-59: LINK ENTRY.......................................................................................................... 638

FIGURE 7-60: LINK DESCRIPTION REGISTER ............................................................................... 639

FIGURE 7-61: LINK ADDRESS FOR LINK TYPE 0.......................................................................... 640

FIGURE 7-62: LINK ADDRESS FOR LINK TYPE 1.......................................................................... 641

FIGURE 7-63: ROOT COMPLEX INTERNAL LINK CONTROL CAPABILITY...................................... 642

FIGURE 7-64: ROOT INTERNAL LINK CONTROL EXTENDED CAPABILITY HEADER...................... 642

FIGURE 7-65: ROOT COMPLEX LINK CAPABILITIES REGISTER .................................................... 643

FIGURE 7-66: ROOT COMPLEX LINK CONTROL REGISTER .......................................................... 645

FIGURE 7-67: ROOT COMPLEX LINK STATUS REGISTER.............................................................. 647

FIGURE 7-68: PCI EXPRESS POWER BUDGETING CAPABILITY STRUCTURE................................. 648

FIGURE 7-69: POWER BUDGETING EXTENDED CAPABILITY HEADER.......................................... 648

IGURE 7-70: POWER BUDGETING DATA REGISTER.................................................................... 650

FIGURE 7-71: POWER BUDGET CAPABILITY REGISTER ............................................................... 652

IGURE 7-72: ACS EXTENDED CAPABILITY................................................................................ 652

IGURE 7-73: ACS EXTENDED CAPABILITY HEADER ................................................................. 653

FIGURE 7-74: ACS CAPABILITY REGISTER................................................................................. 653

FIGURE 7-75: ACS CONTROL REGISTER .................................................................................... 655

IGURE 7-76: EGRESS CONTROL VECTOR REGISTER................................................................... 657

FIGURE 7-77: ROOT COMPLEX EVENT COLLECTOR ENDPOINT ASSOCIATION CAPABILITY......... 658

IGURE 7-78: ROOT COMPLEX EVENT COLLECTOR ENDPOINT ASSOCIATION EXTENDED

CAPABILITY HEADER........................................................................................................... 659

FIGURE 7-79: PCI EXPRESS MFVC CAPABILITY STRUCTURE..................................................... 660

IGURE 7-80: MFVC EXTENDED CAPABILITY HEADER.............................................................. 661

FIGURE 7-81: PORT VC CAPABILITY REGISTER 1 ....................................................................... 662

IGURE 7-82: PORT VC CAPABILITY REGISTER 2 ....................................................................... 664

IGURE 7-83: PORT VC CONTROL REGISTER .............................................................................. 665

IGURE 7-84: PORT VC STATUS REGISTER ................................................................................. 666

PCI EXPRESS BASE SPECIFICATION, REV. 23.0, VER. 0.5

FIGURE 7-85: VC RESOURCE CAPABILITY REGISTER.................................................................. 666

FIGURE 7-86: VC RESOURCE CONTROL REGISTER...................................................................... 668

FIGURE 7-87: VC RESOURCE STATUS REGISTER......................................................................... 670

IGURE 7-88: PCI EXPRESS VSEC STRUCTURE.......................................................................... 674

IGURE 7-89: VENDOR-SPECIFIC EXTENDED CAPABILITY HEADER ............................................ 674

FIGURE 7-90: VENDOR-SPECIFIC HEADER .................................................................................. 676

FIGURE 7-91: ROOT COMPLEX FEATURES CAPABILITY STRUCTURE........................................... 677

FIGURE 7-92: RCRB HEADER EXTENDED CAPABILITY HEADER ................................................ 677

IGURE 7-93: VENDOR ID AND DEVICE ID ................................................................................. 678

IGURE 7-94: RCRB CAPABILITIES ............................................................................................ 679

FIGURE 7-95: RCRB CONTROL................................................................................................... 679

FIGURE 7-96: MULTICAST EXTENDED CAPABILITY STRUCTURE................................................. 681

FIGURE 7-97: MULTICAST EXTENDED CAPABILITY HEADER ...................................................... 681

IGURE 7-98: MULTICAST CAPABILITY REGISTER ...................................................................... 682

IGURE 7-99: MULTICAST CONTROL REGISTER .......................................................................... 683

FIGURE 7-100: MC_BASE_ADDRESS REGISTER ......................................................................... 684

FIGURE 7-101: MC_RECEIVE REGISTER ..................................................................................... 685

FIGURE 7-102: MC_BLOCK_ALL REGISTER............................................................................... 685

FIGURE 7-103: MC_BLOCK_UNTRANSLATED REGISTER............................................................ 686

FIGURE 7-104: MC_OVERLAY_BAR.......................................................................................... 687

FIGURE 7-105: RESIZABLE BAR CAPABILITY............................................................................. 689

FIGURE 7-106: RESIZABLE BAR EXTENDED CAPABILITY HEADER............................................. 689

FIGURE 7-107: RESIZABLE BAR CAPABILITY REGISTER............................................................. 690

FIGURE 7-108: RESIZABLE BAR CONTROL REGISTER ................................................................ 692

FIGURE 7-109: ARI CAPABILITY................................................................................................. 694

FIGURE 7-110: ARI CAPABILITY HEADER .................................................................................. 694

FIGURE 7-111: ARI CAPABILITY REGISTER ................................................................................ 695

FIGURE 7-112: ARI CONTROL REGISTER .................................................................................... 696

FIGURE 7-113: DYNAMIC POWER ALLOCATION CAPABILITY STRUCTURE .................................. 697

FIGURE 7-114: DPA EXTENDED CAPABILITY HEADER ............................................................... 698

IGURE 7-115: DPA CAPABILITY REGISTER ............................................................................... 699

FIGURE 7-116: DPA LATENCY INDICATOR REGISTER................................................................. 700

IGURE 7-117: DPA STATUS REGISTER ...................................................................................... 700

IGURE 7-118: DPA CONTROL REGISTER ................................................................................... 701

FIGURE 7-119: DPA POWER ALLOCATION ARRAY ..................................................................... 701

FIGURE 7-120: LTR EXTENDED CAPABILITY STRUCTURE .......................................................... 702

IGURE 7-121: LTR EXTENDED CAPABILITY HEADER................................................................ 702

FIGURE 7-122: MAX SNOOP LATENCY REGISTER ....................................................................... 703

IGURE 7-123: MAX NO-SNOOP LATENCY REGISTER................................................................. 704

FIGURE A-1: AN EXAMPLE SHOWING ENDPOINT-TO-ROOT-COMPLEX AND PEER-TO-PEER

COMMUNICATION MODELS.................................................................................................. 706

IGURE A-2: TWO BASIC BANDWIDTH RESOURCING PROBLEMS: OVER-SUBSCRIPTION AND

CONGESTION........................................................................................................................ 707

IGURE A-3: A SIMPLIFIED EXAMPLE ILLUSTRATING PCI EXPRESS ISOCHRONOUS PARAMETERS

............................................................................................................................................. 712

IGURE C-1: SCRAMBLING SPECTRUM FOR DATA VALUE OF 0................................................... 731

PCI EXPRESS BASE SPECIFICATION, REV. 23.0, VER. 0.5

FIGURE E-1: REFERENCE TOPOLOGY FOR IDO USE .................................................................... 737

Tables

TABLE 2-1: TRANSACTION TYPES FOR DIFFERENT ADDRESS SPACES........................................... 50

TABLE 2-2: FMT[1:0] FIELD VALUES ............................................................................................ 54

ABLE 2-3: FMT[1:0] AND TYPE[4:0] FIELD ENCODINGS.............................................................. 55

ABLE 2-4: LENGTH[9:0] FIELD ENCODING .................................................................................. 56

TABLE 2-5: ADDRESS TYPE (AT) FIELD ENCODINGS .................................................................... 62

TABLE 2-6: ADDRESS FIELD MAPPING.......................................................................................... 62

TABLE 2-7: HEADER FIELD LOCATIONS FOR (NON-ARI) ID ROUTING .......................................... 63

ABLE 2-8: HEADER FIELD LOCATIONS FOR ARI ID ROUTING..................................................... 63

ABLE 2-9: BYTE ENABLES LOCATION AND CORRESPONDENCE................................................... 66

TABLE 2-10: ORDERING ATTRIBUTES ........................................................................................... 71

TABLE 2-11: CACHE COHERENCY MANAGEMENT ATTRIBUTE...................................................... 71

TABLE 2-12: DEFINITION OF TC FIELD ENCODINGS...................................................................... 72

TABLE 2-13: LENGTH FIELD VALUES FOR ATOMICOP REQUESTS................................................. 73

TABLE 2-14: MESSAGE ROUTING.................................................................................................. 79

TABLE 2-15: INTX MECHANISM MESSAGES ................................................................................. 80

TABLE 2-16: BRIDGE MAPPING FOR INTX VIRTUAL WIRES ......................................................... 82

TABLE 2-17: POWER MANAGEMENT MESSAGES........................................................................... 84

TABLE 2-18: ERROR SIGNALING MESSAGES ................................................................................. 85

TABLE 2-19 UNLOCK MESSAGE.................................................................................................... 86

TABLE 2-20: SET_SLOT_POWER_LIMIT MESSAGE ....................................................................... 86

TABLE 2-21: VENDOR_DEFINED MESSAGES................................................................................. 87

TABLE 2-22: IGNORED MESSAGES ................................................................................................ 89

TABLE 2-23: LTR MESSAGE ......................................................................................................... 90

TABLE 2-24: COMPLETION STATUS FIELD VALUES....................................................................... 92

TABLE 2-25: CALCULATING BYTE COUNT FROM LENGTH AND BYTE ENABLES.......................... 107

TABLE 2-26: CALCULATING LOWER ADDRESS FROM 1

DW BE............................................... 108

TABLE 2-27: ORDERING RULES SUMMARY ................................................................................. 113

ABLE 2-28: TC TO VC MAPPING EXAMPLE .............................................................................. 122

TABLE 2-29: FLOW CONTROL CREDIT TYPES ............................................................................. 126

ABLE 2-30: TLP FLOW CONTROL CREDIT CONSUMPTION ........................................................ 126

ABLE 2-31: MINIMUM INITIAL FLOW CONTROL ADVERTISEMENTS .......................................... 127

TABLE 2-32: UPDATEFC TRANSMISSION LATENCY GUIDELINES FOR 2.5 GT/S MODE OPERATION

LINK WIDTH AND MAX PAYLOAD (SYMBOL TIMES) ...................................................... 135

ABLE 2-33: UPDATEFC TRANSMISSION LATENCY GUIDELINES FOR 5.0 GT/S MODE OPERATION

LINK WIDTH AND MAX PAYLOAD (SYMBOL TIMES) ...................................................... 135

TABLE 2-34: MAPPING OF BITS INTO ECRC FIELD ..................................................................... 137

ABLE 3-1: DLLP TYPE ENCODINGS.......................................................................................... 155

TABLE 3-2: MAPPING OF BITS INTO CRC FIELD.......................................................................... 158

ABLE 3-3: MAPPING OF BITS INTO LCRC FIELD ....................................................................... 162

TABLE 3-4: UNADJUSTED REPLAY_TIMER LIMITS FOR 2.5 GT/S MODE OPERATION BY LINK

WIDTH AND MAX_PAYLOAD_SIZE (SYMBOL TIMES) TOLERANCE: -0%/+100%................. 166

PCI EXPRESS BASE SPECIFICATION, REV. 23.0, VER. 0.5

TABLE 3-5: UNADJUSTED REPLAY_TIMER LIMITS FOR 5.0 GT/S MODE OPERATION BY LINK

WIDTH AND MAX_PAYLOAD_SIZE (SYMBOL TIMES) TOLERANCE: -0%/+100%................. 167

TABLE 3-6: ACK TRANSMISSION LATENCY LIMIT AND ACKFACTOR FOR 2.5 GT/S MODE

OPERATION BY LINK WIDTH AND MAX PAYLOAD (SYMBOL TIMES)................................... 177

ABLE 3-7: ACK TRANSMISSION LATENCY LIMIT AND ACKFACTOR FOR 5.0 GT/S MODE

OPERATION BY LINK WIDTH AND MAX PAYLOAD (SYMBOL TIMES)................................... 177

TABLE 4-1: PCI EXPRESS 2.5 GT/S / 5.0 GT/S INTEROPERABILITY MATRIX ............................... 275

TABLE 4-2: 2.5 AND 5.0 GT/S TRANSMITTER SPECIFICATIONS ................................................... 281

ABLE 4-3: 5.0 GT/S TOLERANCING LIMITS FOR COMMON REFCLK RX ARCHITECTURE............ 296

ABLE 4-4: 5.0 GT/S TOLERANCING LIMITS FOR DATA CLOCKED RX ARCHITECTURE.............. 297

TABLE 4-5: 2.5 AND 5.0 GT/S RECEIVER SPECIFICATIONS .......................................................... 299

TABLE 4-6: WORST CASE TX CORNERS FOR CHANNEL SIMULATION.......................................... 315

TABLE 4-7: FILTERING FUNCTIONS APPLIED TO REFCLK MEASUREMENTS ................................ 320

ABLE 4-8: DIFFERENCE FUNCTION PARAMETERS APPLIED TO REFCLK MEASUREMENT ........... 322

ABLE 4-9: REFCLK PARAMETERS FOR COMMON REFCLK RX ARCHITECTURE AT 5.0 GT/S....... 322

TABLE 4-10: PLL PARAMETERS FOR DATA CLOCKED RX ARCHITECTURE ................................. 324

TABLE 4-11: REFCLK PARAMETERS FOR DATA CLOCKED RX ARCHITECTURE ........................... 324

TABLE 4-12: REFERENCE PLANE INDEPENDENT TRANSMITTER PARAMETERS............................. 329

TABLE 4-13: REFERENCE PLANE DEPENDENT TX PARAMETERS.................................................. 331

TABLE 4-14: COMMON REFCLK RX COMPLIANCE PARAMETERS .................................................. 339

TABLE 4-15: DATA CLOCKED RX COMPLIANCE PARAMETERS ..................................................... 341

TABLE 4-16: STATIC RX PARAMETERS ........................................................................................ 344

TABLE 4-17: TX PACKAGE/DIE PARASITICS PARAMETER RANGES................................................. 348

TABLE 4-18: RX PACKAGE/DIE PARASITICS PARAMETER RANGES ................................................ 348

TABLE 4-19: CHANNEL VALIDATION PARAMETERS..................................................................... 349

TABLE 4-20: REA PARAMETERS.................................................................................................. 351

TABLE 4-21: RX PARAMETERS FOR CHANNEL TOLERANCING ..................................................... 352

TABLE 5-1: SUMMARY OF PCI EXPRESS LINK POWER MANAGEMENT STATES........................... 362

TABLE 5-2: RELATION BETWEEN POWER MANAGEMENT STATES OF LINK AND COMPONENTS .. 367

TABLE 5-3: ENCODING OF THE ASPM SUPPORT FIELD ............................................................... 392

ABLE 5-4: DESCRIPTION OF THE SLOT CLOCK CONFIGURATION BIT......................................... 393

TABLE 5-5: DESCRIPTION OF THE COMMON CLOCK CONFIGURATION BIT .................................. 393

ABLE 5-6: ENCODING OF THE L0S EXIT LATENCY FIELD .......................................................... 393

ABLE 5-7: ENCODING OF THE L1 EXIT LATENCY FIELD ............................................................ 394

TABLE 5-8: ENCODING OF THE ENDPOINT L0S ACCEPTABLE LATENCY FIELD............................ 394

TABLE 5-9: ENCODING OF THE ENDPOINT L1 ACCEPTABLE LATENCY FIELD.............................. 394

ABLE 5-10: ENCODING OF THE ASPM CONTROL FIELD............................................................ 395

TABLE 5-11: POWER MANAGEMENT SYSTEM MESSAGES AND DLLPS ....................................... 397

ABLE 6-1: ERROR MESSAGES.................................................................................................... 407

TABLE 6-2: GENERAL PCI EXPRESS ERROR LIST......................................................................... 421

TABLE 6-3: PHYSICAL LAYER ERROR LIST ................................................................................. 421

ABLE 6-4: DATA LINK LAYER ERROR LIST............................................................................... 422

TABLE 6-5: TRANSACTION LAYER ERROR LIST .......................................................................... 423

ABLE 6-6: ELEMENTS OF HOT-PLUG ......................................................................................... 453

ABLE 6-7: ATTENTION INDICATOR STATES ............................................................................... 454

ABLE 6-8: POWER INDICATOR STATES ...................................................................................... 455

PCI EXPRESS BASE SPECIFICATION, REV. 23.0, VER. 0.5

TABLE 6-9: ACS P2P REQUEST REDIRECT AND ACS P2P EGRESS CONTROL INTERACTIONS..... 477

TABLE 6-10: ECRC RULES FOR MC_OVERLAY ......................................................................... 489

TABLE 7-1: ENHANCED CONFIGURATION ADDRESS MAPPING .................................................... 515

ABLE 7-2: REGISTER AND REGISTER BIT-FIELD TYPES............................................................. 522

ABLE 7-3: COMMAND REGISTER ............................................................................................... 525

TABLE 7-4: STATUS REGISTER .................................................................................................... 527

TABLE 7-5: SECONDARY STATUS REGISTER ............................................................................... 533

TABLE 7-6: BRIDGE CONTROL REGISTER.................................................................................... 535

ABLE 7-7: POWER MANAGEMENT CAPABILITIES REGISTER ADDED REQUIREMENTS ............... 536

ABLE 7-8: POWER MANAGEMENT STATUS/CONTROL REGISTER ADDED REQUIREMENTS ........ 537

TABLE 7-9: PCI EXPRESS CAPABILITY LIST REGISTER ............................................................... 540

TABLE 7-10: PCI EXPRESS CAPABILITIES REGISTER................................................................... 540

TABLE 7-11: DEVICE CAPABILITIES REGISTER............................................................................ 543

ABLE 7-12: DEVICE CONTROL REGISTER.................................................................................. 548

ABLE 7-13: DEVICE STATUS REGISTER ..................................................................................... 554

TABLE 7-14: LINK CAPABILITIES REGISTER................................................................................ 556

TABLE 7-15: LINK CONTROL REGISTER ...................................................................................... 561

TABLE 7-16: LINK STATUS REGISTER ......................................................................................... 568

TABLE 7-17: SLOT CAPABILITIES REGISTER ............................................................................... 571

TABLE 7-18: SLOT CONTROL REGISTER...................................................................................... 574

TABLE 7-19: SLOT STATUS REGISTER......................................................................................... 577

TABLE 7-20: ROOT CONTROL REGISTER..................................................................................... 579

TABLE 7-21: ROOT CAPABILITIES REGISTER............................................................................... 581

TABLE 7-22: ROOT STATUS REGISTER........................................................................................ 582

TABLE 7-23: DEVICE CAPABILITIES 2 REGISTER......................................................................... 584

TABLE 7-24: DEVICE CONTROL 2 REGISTER................................................................................ 588

TABLE 7-25: LINK CONTROL 2 REGISTER ................................................................................... 591

TABLE 7-26: LINK STATUS 2 REGISTER ...................................................................................... 595

TABLE 7-27: PCI EXPRESS EXTENDED CAPABILITY HEADER ..................................................... 597

TABLE 7-28: ADVANCED ERROR REPORTING EXTENDED CAPABILITY HEADER......................... 599

ABLE 7-29: UNCORRECTABLE ERROR STATUS REGISTER ......................................................... 601

TABLE 7-30: UNCORRECTABLE ERROR MASK REGISTER............................................................ 602

ABLE 7-31: UNCORRECTABLE ERROR SEVERITY REGISTER ...................................................... 605

ABLE 7-32: CORRECTABLE ERROR STATUS REGISTER.............................................................. 606

TABLE 7-33: CORRECTABLE ERROR MASK REGISTER................................................................. 608

TABLE 7-34: ADVANCED ERROR CAPABILITIES AND CONTROL REGISTER.................................. 609

ABLE 7-35: HEADER LOG REGISTER ......................................................................................... 611

TABLE 7-36: ROOT ERROR COMMAND REGISTER ....................................................................... 612

ABLE 7-37: ROOT ERROR STATUS REGISTER ............................................................................ 614

TABLE 7-38: ERROR SOURCE IDENTIFICATION REGISTER ........................................................... 616

TABLE 7-39: VIRTUAL CHANNEL EXTENDED CAPABILITY HEADER ........................................... 619

ABLE 7-40: PORT VC CAPABILITY REGISTER 1......................................................................... 620

TABLE 7-41: PORT VC CAPABILITY REGISTER 2......................................................................... 622

ABLE 7-42: PORT VC CONTROL REGISTER ............................................................................... 623

ABLE 7-43: PORT VC STATUS REGISTER .................................................................................. 624

ABLE 7-44: VC RESOURCE CAPABILITY REGISTER................................................................... 625

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