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ADSP-CM40x 混合信号控制处理器官方手册
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更新于2024-07-21
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"ADI公司CM40X系列官方芯片手册,主要介绍ADSP-CM40x混合信号控制处理器,该处理器基于ARM Cortex-M4内核。文档为硬件参考初步修订版0.2,发布于2013年9月。"
ADSP-CM40x系列是由ADI(Analog Devices, Inc.)推出的混合信号控制处理器,其核心是高效的32位ARM Cortex-M4处理器。ARM Cortex-M4是一款广泛应用的微控制器内核,具有浮点运算单元(FPU),适用于需要高性能计算和低功耗操作的嵌入式应用。该系列芯片集成了模拟和数字功能,使其在处理复杂的混合信号系统时表现出色,例如在工业自动化、汽车电子、医疗设备以及消费类电子产品等领域。
手册内容可能包括以下几个关键部分:
1. **架构与特性**:详细介绍了ADSP-CM40x的体系结构,包括CPU内核、内存组织、外设接口、中断系统等。Cortex-M4内核支持单指令多数据(SIMD)指令,提供快速的数学运算能力,同时具备调试和跟踪功能,便于开发和调试。
2. **模拟功能**:ADSP-CM40x可能内置了模拟电路,如ADC(模数转换器)、DAC(数模转换器)、 PGA(可编程增益放大器)等,这些模拟接口使得处理器可以直接与传感器和其他模拟信号源交互。
3. **数字外设**:通常会涵盖GPIO(通用输入/输出)、UART(通用异步接收发送器)、SPI(串行外围接口)、I2C(集成电路间通信)等常用通信接口,以及定时器、PWM(脉宽调制)模块等。
4. **电源管理与功耗**:介绍如何配置和管理处理器的电源模式,以优化性能和节能。
5. **开发工具与生态系统**:可能提及ADI提供的开发工具,如VisualDSP++和CrossCore Embedded Studio,这些工具集成了编译器、调试器和性能分析器,帮助开发者进行高效编程和性能优化。
6. **应用示例**:可能包含一些典型的应用场景和示例代码,帮助用户理解如何在实际项目中使用ADSP-CM40x。
7. **封装与引脚配置**:详述芯片的不同封装形式和引脚定义,以及在电路板设计时的注意事项。
8. **电气特性与兼容性**:列出芯片的电气参数,如工作电压范围、工作温度范围等,确保与外部组件的兼容性。
9. **安全与认证**:可能涉及产品的安全性标准,如EMC(电磁兼容性)和安规认证。
10. **技术支持与更新**:提供获取最新信息和支持的途径,包括更新版本的文档、软件库和固件更新。
注意,由于手册是初步修订版0.2,可能并未包含所有最终的功能和细节,使用者应关注ADI官方网站获取最新的产品信息和技术更新。此外,手册中的免责声明指出,ADI保留随时更改产品而不事先通知的权利,并且对于使用手册信息可能导致的任何专利侵权或其他第三方权利侵犯不承担责任,同时也明确表示不授予任何暗示的专利使用权。
CONTENTS
xvi ADSP-CM40X MIXED-SIGNAL CONTROL PROCESSOR WITH ARM CORTEX-M4 HARDWARE REFERENCE
DMA Driven Memory Scan Compute Compare Mode ........................................................................ 10-15
Core Driven Memory Scan Data Verify Mode ..................................................................................... 10-17
DMA Driven Memory Scan Data Verify Mode ................................................................................... 10-19
Core Driven Memory Transfer Compute Compare Mode .................................................................... 10-20
DMA Driven Memory Transfer Compute Compare Mode .................................................................. 10-22
DMA Driven Memory Transfer Data Fill Mode .................................................................................. 10-24
ADSP-CM40x CRC Peripheral and DMA Channel List ............................................................................ 10-25
ADSP-CM40x CRC Register Descriptions ............................................................................................... 10-26
Control Register ...................................................................................................................................... 10-26
Data Word Count Register ...................................................................................................................... 10-29
Data Word Count Reload Register ......................................................................................................... 10-30
Data Compare Register ........................................................................................................................... 10-31
Fill Value Register .................................................................................................................................. 10-31
Data FIFO Register ................................................................................................................................. 10-32
Interrupt Enable Register ........................................................................................................................ 10-33
Interrupt Enable Set Register .................................................................................................................. 10-34
Interrupt Enable Clear Register .............................................................................................................. 10-34
Polynomial Register ................................................................................................................................ 10-35
Status Register ........................................................................................................................................ 10-36
Data Count Capture Register .................................................................................................................. 10-38
CRC Final Result Register ...................................................................................................................... 10-38
CRC Current Result Register .................................................................................................................. 10-39
Direct Memory Access (DMA)
DMA Channel Features ................................................................................................................................ 11-1
DMA Channel Functional Description ......................................................................................................... 11-3
ADSP-CM40x DMA Register List ............................................................................................................ 11-3
DMA Definitions ....................................................................................................................................... 11-4
Block Diagram ........................................................................................................................................... 11-5
SCB Interface Signals ............................................................................................................................ 11-7
DMA Channel Peripheral DMA Bus ...................................................................................................... 11-7
CONTENTS
ADSP-CM40X MIXED-SIGNAL CONTROL PROCESSOR WITH ARM CORTEX-M4 HARDWARE REFERENCE xvii
DMA Channel MMR Access Bus .......................................................................................................... 11-8
Event Signals .......................................................................................................................................... 11-8
Architectural Concepts .............................................................................................................................. 11-8
DMA Channel SCB Interface ................................................................................................................. 11-8
SCB Interface Signals ......................................................................................................................... 11-9
SCB Burst Transfers ........................................................................................................................... 11-9
Data Address Alignment .................................................................................................................... 11-10
Descriptor Set Address Alignment ................................................................................................... 11-10
DMA Channel Peripheral DMA Bus .................................................................................................... 11-11
Peripheral Control Commands ........................................................................................................... 11-11
Peripheral Control Command Restrictions ........................................................................................ 11-14
Memory DMA and Triggering ............................................................................................................. 11-15
DMA Channel MMR Access Bus ........................................................................................................ 11-17
DMA Channel Operation Flow ............................................................................................................. 11-17
Startup ................................................................................................................................................ 11-17
Refresh ............................................................................................................................................... 11-19
Work Unit Transitions ....................................................................................................................... 11-20
Transfer Termination and Shutdown ................................................................................................. 11-22
DMA Channel Errors ............................................................................................................................ 11-24
Status and Debug ............................................................................................................................... 11-24
DMA Configuration Register Errors ................................................................................................ 11-25
Illegal Register Write During Run ..................................................................................................... 11-25
Address Alignment Error ................................................................................................................... 11-25
Memory Access Error ....................................................................................................................... 11-25
Trigger Overrun Error ....................................................................................................................... 11-25
Bandwidth Monitor Error ................................................................................................................. 11-26
Control Interface Error ...................................................................................................................... 11-26
DMA Operating Modes .............................................................................................................................. 11-26
Register Based Flow Modes ................................................................................................................... 11-26
Stop Mode ............................................................................................................................................. 11-27
CONTENTS
xviii ADSP-CM40X MIXED-SIGNAL CONTROL PROCESSOR WITH ARM CORTEX-M4 HARDWARE REFERENCE
Autobuffer Mode .................................................................................................................................. 11-27
Descriptor Based Flow Modes ................................................................................................................ 11-27
Descriptor Array Mode ......................................................................................................................... 11-28
Descriptor List Mode ............................................................................................................................ 11-28
Descriptor Sets ................................................................................................................................... 11-28
Minimum Startup Requirements ........................................................................................................ 11-29
Descriptor On-Demand Modes ............................................................................................................. 11-29
Data Transfer Modes ................................................................................................................................ 11-30
Two-Dimensional DMA ....................................................................................................................... 11-30
DMA Channel Event Control ..................................................................................................................... 11-31
Event Signals ........................................................................................................................................... 11-32
Work Unit State Events .......................................................................................................................... 11-32
Peripheral Interrupt Request Events ....................................................................................................... 11-33
Peripheral Data Request Events ............................................................................................................... 11-33
DMA Channel Triggers .......................................................................................................................... 11-33
Issuing Triggers ...................................................................................................................................... 11-34
Waiting For Triggers .............................................................................................................................. 11-34
DMA Channel Programming Model .......................................................................................................... 11-35
Mode Configuration ................................................................................................................................. 11-35
Register Based Linear Buffer Stop Flow Mode ................................................................................... 11-36
Register Based Autobuffer Flow Mode ............................................................................................... 11-37
Descriptor Array Flow Mode ................................................................................................................ 11-38
Descriptor List Flow Mode ................................................................................................................... 11-39
Register Based Memory-to-Memory Transfer in Stop Flow Mode ...................................................... 11-40
Programming Concepts ............................................................................................................................ 11-41
Synchronization of Software and DMA ............................................................................................... 11-41
Interrupt and Trigger Event Based Synchronization ......................................................................... 11-42
Register Polling Based Synchronization ............................................................................................ 11-42
Descriptor Queues ................................................................................................................................. 11-42
Queues Using Event Generation for Every Descriptor Set ................................................................ 11-43
CONTENTS
ADSP-CM40X MIXED-SIGNAL CONTROL PROCESSOR WITH ARM CORTEX-M4 HARDWARE REFERENCE xix
Queues Using Minimal Events .......................................................................................................... 11-44
ADSP-CM40x DMA Register Descriptions .............................................................................................. 11-45
Pointer to Next Initial Descriptor ............................................................................................................ 11-46
Start Address of Current Buffer .............................................................................................................. 11-47
Configuration Register ............................................................................................................................ 11-47
Inner Loop Count Start Value ................................................................................................................. 11-54
Inner Loop Address Increment ............................................................................................................... 11-54
Outer Loop Count Start Value (2D only) ............................................................................................... 11-55
Outer Loop Address Increment (2D only) .............................................................................................. 11-56
Current Descriptor Pointer ...................................................................................................................... 11-56
Previous Initial Descriptor Pointer ......................................................................................................... 11-57
Current Address ...................................................................................................................................... 11-58
Status Register ........................................................................................................................................ 11-59
Current Count(1D) or intra-row XCNT (2D) ......................................................................................... 11-62
Current Row Count (2D only) ................................................................................................................ 11-63
Bandwidth Limit Count .......................................................................................................................... 11-63
Bandwidth Limit Count Current ............................................................................................................. 11-64
Bandwidth Monitor Count ...................................................................................................................... 11-65
Bandwidth Monitor Count Current ......................................................................................................... 11-65
General-Purpose Ports (PORT)
PORT Features .............................................................................................................................................. 12-2
PORT Functional Description ...................................................................................................................... 12-2
ADSP-CM40x PORT Register List ........................................................................................................... 12-2
ADSP-CM40x PORT 120-PIN LQFP_EP GP I/O Multiplexing .............................................................. 12-3
ADSP-CM40x PORT 176-PIN LQFP_EP GP I/O Multiplexing .............................................................. 12-6
ADSP-CM40x PINT Register List .......................................................................................................... 12-10
ADSP-CM40x PINT Interrupt List .......................................................................................................... 12-11
ADSP-CM40x PINT Trigger List ............................................................................................................ 12-11
ADSP-CM40x PADS Register List ......................................................................................................... 12-11
PORT Definitions .................................................................................................................................... 12-12
CONTENTS
xx ADSP-CM40X MIXED-SIGNAL CONTROL PROCESSOR WITH ARM CORTEX-M4 HARDWARE REFERENCE
PORT Architectural Concepts ................................................................................................................. 12-12
Internal Interfaces ................................................................................................................................ 12-12
External Interfaces ................................................................................................................................ 12-12
GPIO Functionality ............................................................................................................................... 12-12
Input Mode ......................................................................................................................................... 12-12
Output Mode ..................................................................................................................................... 12-13
Open-Drain Mode ............................................................................................................................. 12-13
Port Multiplexing Control ..................................................................................................................... 12-13
PORT Event Control ................................................................................................................................... 12-14
PORT Interrupt Signals ........................................................................................................................... 12-14
PORT Programming Model ........................................................................................................................ 12-16
ADSP-CM40x PORT Register Descriptions ............................................................................................. 12-19
Port x Function Enable Register ............................................................................................................. 12-20
Port x Function Enable Set Register ....................................................................................................... 12-23
Port x Function Enable Clear Register ................................................................................................... 12-25
Port x GPIO Data Register ...................................................................................................................... 12-28
Port x GPIO Data Set Register ............................................................................................................... 12-31
Port x GPIO Data Clear Register ............................................................................................................ 12-34
Port x GPIO Direction Register .............................................................................................................. 12-38
Port x GPIO Direction Set Register ........................................................................................................ 12-42
Port x GPIO Direction Clear Register .................................................................................................... 12-44
Port x GPIO Input Enable Register ......................................................................................................... 12-47
Port x GPIO Input Enable Set Register .................................................................................................. 12-50
Port x GPIO Input Enable Clear Register ............................................................................................... 12-53
Port x Multiplexer Control Register ....................................................................................................... 12-56
Port x GPIO Input Enable Toggle Register ............................................................................................ 12-58
Port x GPIO Polarity Invert Register ...................................................................................................... 12-61
Port x GPIO Polarity Invert Set Register ................................................................................................ 12-65
Port x GPIO Polarity Invert Clear Register ............................................................................................ 12-67
Port x GPIO Lock Register ..................................................................................................................... 12-70
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