CONTENTS
xx ADSP-CM40X MIXED-SIGNAL CONTROL PROCESSOR WITH ARM CORTEX-M4 HARDWARE REFERENCE
PORT Architectural Concepts ................................................................................................................. 12-12
Internal Interfaces ................................................................................................................................ 12-12
External Interfaces ................................................................................................................................ 12-12
GPIO Functionality ............................................................................................................................... 12-12
Input Mode ......................................................................................................................................... 12-12
Output Mode ..................................................................................................................................... 12-13
Open-Drain Mode ............................................................................................................................. 12-13
Port Multiplexing Control ..................................................................................................................... 12-13
PORT Event Control ................................................................................................................................... 12-14
PORT Interrupt Signals ........................................................................................................................... 12-14
PORT Programming Model ........................................................................................................................ 12-16
ADSP-CM40x PORT Register Descriptions ............................................................................................. 12-19
Port x Function Enable Register ............................................................................................................. 12-20
Port x Function Enable Set Register ....................................................................................................... 12-23
Port x Function Enable Clear Register ................................................................................................... 12-25
Port x GPIO Data Register ...................................................................................................................... 12-28
Port x GPIO Data Set Register ............................................................................................................... 12-31
Port x GPIO Data Clear Register ............................................................................................................ 12-34
Port x GPIO Direction Register .............................................................................................................. 12-38
Port x GPIO Direction Set Register ........................................................................................................ 12-42
Port x GPIO Direction Clear Register .................................................................................................... 12-44
Port x GPIO Input Enable Register ......................................................................................................... 12-47
Port x GPIO Input Enable Set Register .................................................................................................. 12-50
Port x GPIO Input Enable Clear Register ............................................................................................... 12-53
Port x Multiplexer Control Register ....................................................................................................... 12-56
Port x GPIO Input Enable Toggle Register ............................................................................................ 12-58
Port x GPIO Polarity Invert Register ...................................................................................................... 12-61
Port x GPIO Polarity Invert Set Register ................................................................................................ 12-65
Port x GPIO Polarity Invert Clear Register ............................................................................................ 12-67
Port x GPIO Lock Register ..................................................................................................................... 12-70