SRAM FPGA故障容错技术

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"Fault-Tolerance Techniques for SRAM-based FPGAs" 是一本专注于在基于静态随机访问内存（SRAM）的现场可编程门阵列（FPGA）中实现故障诊断和容错控制技术的书籍。这本书由Fernanda Lima Kastensmidt、Luigi Carro、Ricardo Reis等人撰写，并作为“前沿电子测试”系列的一部分，由Vishwani D. Agrawal担任咨询编辑。该系列还包括其他几本关于电子测试、嵌入式处理器自测、错误建模验证以及STIL（系统测试接口语言）原理和应用等主题的著作。在FPGA设计中，SRAM是用于存储配置逻辑的常用技术，因为它们可以快速重配置并提供高度的灵活性。然而，这种灵活性也带来了固有的不稳定性，尤其是在面临辐射、温度变化、制造缺陷或老化效应时，这些都可能导致SRAM位翻转，进而影响FPGA的功能。因此，故障诊断和容错控制对于确保SRAM-based FPGA的可靠性和鲁棒性至关重要。该书可能涵盖了以下关键知识点： 1. **故障模型**：书中可能会讨论不同的故障类型，如单事件翻转（SET）、单事件功耗翻转（SEU）、多位错误等，这些都是在高辐射环境或高速操作中常见的问题。 2. **检测和纠正机制**：介绍用于检测和纠正错误的技术，如奇偶校验、双冗余、循环冗余校验（CRC）、纠错码（ECC），如BCH码和汉明码，以及更复杂的前向错误更正（FEC）方案。 3. **自修复逻辑**：可能包括自检测、自修复（BIST和BIT）策略，使得FPGA能够识别并自动修复内部故障。 4. **容错架构**：书中可能会探讨如何通过硬件冗余、故障隔离和恢复机制来设计容错的FPGA架构，如部分动态重构和故障屏蔽。 5. **测试方法**：介绍有效的测试策略，如扫描测试、边界扫描、系统级测试，以及针对SRAM-based FPGA的专用测试算法。 6. **性能与功耗权衡**：容错技术往往会影响性能和功耗，因此书中可能会讨论如何在保证可靠性的同时优化这些指标。 7. **应用案例**：书中可能会提供实际应用场景，如航空航天、军事、医疗设备和数据中心，其中对FPGA的高可靠性有严格要求。 8. **工具和技术**：介绍用于故障模拟、故障注入和容错设计的软件工具，以及相关的设计流程和最佳实践。通过深入学习这本书，读者可以获取到如何在SRAM-based FPGA设计中实施高效且实用的容错控制策略的知识，从而提高系统的整体可靠性。这将对那些在高可靠性领域工作的工程师和研究人员特别有价值。

2 Chapter 1

amount of embedded memories, followed by an amazing scaling down

process of transistor dimensions following Moore’s Law (Moore, 1975).

The fabrication technology process of semiconductor components is in

continuous evolution in terms of transistor geometry shrinking, power

supply, speed, and logic density (SIA Semiconductor, 1994). As stated in

(Johnston, 2000; Obryan and Label, 2001; Obryan et al., 2002; Dupont

et al., 2002), drastic device shrinking, power supply reduction, and

increasing operating speeds significantly reduce the noise margins, and thus

the reliability that very deep submicron (VDSM) ICs face from the various

internal sources of noise. Reliability is the probability of no failure in a

given operating period. It is used to measure how good a system is and how

frequently it goes down.

The fabrication process is now approaching a point where it will be

unfeasible to produce ICs that are free from upset effects. A more significant

problem is related to SEU. It is predicted that neutrons produced by sun

activity will dramatically affect the operation of future ICs. At the sea level,

the energy of these particles is not strong enough to drastically affect the

operation of current ICs. But as one approaches 0.1µm, or very low supply

voltages, the rate of random errors induced by cosmic neutrons will be

unacceptable. The situation is worse at flight altitudes. Alpha particles

produced by packaging material are becoming another cause of increasing

soft error rates in these technologies (Normand, 2001).

The necessity to protect integrated circuits against upsets has become

more and more eminent (Johnston, 2000; Label et al., 2000). Experiments

presented in (Normand and Baker, 1993; Normand, 1996, 2001) indicate that

neutron particles present in the atmosphere are capable of producing SEE in

avionics. Recent studies also show that memory cells composed of

transistors with channel length smaller than 0.25 µm and combinational

logic composed of transistors with length smaller than 0.13 µm may be

subject to upsets while operating in the space environment, or inside the

atmosphere (Baumann, 2001; Borel et al., 2001). Remember that current IC

are been fabricated in 90 nm CMOS technology and below. Terrestrial

applications that are determined as critical such as bank servers,

telecommunication servers and avionics are more and more considering the

use of fault-tolerant techniques to ensure reliability.

Both discussed factors, the space market interest of using COTS/military

devices in space applications and the constant increase in the radiation

sensitivity of integrated circuits driven by the process scaling, have brought

the necessity of researching fault-tolerant techniques for ICs able to cope

with the radiation effects at sea level, and also qualifying the design for

space applications. Based on the definition of fault-tolerance, the goal is to

maintain the IC operating correctly despite the existence of upsets. Although

INTRODUCTION 3

many techniques have been developed in the last few years attempting to

avoid SEU, efficient fault-tolerant solutions are still a challenge for the next

generation semiconductor industry, especially because of the complexity of

the new architectures.

The development of fault-tolerant techniques is strongly associated with

the target device, and it requires a detailed analysis of the effects of an upset

on the related architecture. For each type of circuit, there is a set of most

suitable solutions to be applied. In the past years, the integrated circuit

industry has designed more and more complex architectures in order

to improve performance, to increase logic density and to reduce cost.

Examples of this development include Application Specific Integrated

Circuits (ASICs), microprocessors composed of millions of transistors, high-

density Field Programmable Gate Array (FPGA) components and, more

recently, System-on-a-Chip (SOC) composed of embedded microprocessors,

memories and analog blocks. These architectures have made a dramatic

impact on the way systems are designed, providing a large amount of

information processing on a single chip. They cover a wide range of

applications, from portable systems to dedicated embedded control units and

computers. In particular, FPGAs have made a major improvement in

systems design by adding the reconfigurability feature, which reduces the

time to market and increases the design flexibility.

A set of events have contributed to increase the market for FPGAs

figure 1-1 in the last years. The constant advances in technology over the

last years, following Moore’s law, the gap between FPGAs and ASICs in

terms of performance has been reduced to a negligible level for the majority

of applications. In addition, the cost for low and medium volumes of FPGA

parts has reduced compared to low and medium volumes parts of ASICs.

The time to market, the necessity to speed up the design process and

prototyping, has also increased the need of using programmable logic.

In the 70s, a system was basically composed of a microprocessor

component, a memory chip and discrete logic. In the 80s, a large part of the

discrete logic was replaced by ASICs and some part by programmable logic

components (FPGA). In the 90s, the discrete logic completely disappeared

and the system was composed of microprocessors, memory, ASICs and

FPGA components. ASICs are progressively being replaced by FPGAs in

many systems as illustrated. In addition, more complex structures are

constantly being added to FPGA architectures, supported by substantial

increases in logic density and performance in the last few years. Nowadays,

FPGAs are also replacing microprocessors and memories as these parts are

being added to the FPGA matrix.

Consequently, next generation of FPGA architectures do not claim to

reduce that gap between ASIC and programmable logic anymore, but to

4 Chapter 1

merge microprocessors and reconfigurability features in the same

component in order to improve performance and flexibility (DAC, 2001).

FPGAs already provide reconfigurability and high performance for many

appli-cations, but the necessity of adding either more performance for

applications such as Digital Signal Processing (DSP), using high-bandwidth

and reducing the board space, power and cost, has increased the interest of

embedding microprocessors in the programmable matrix, as illustrated in

more detail in figure 1-2. This experience had started with the soft cores

synthesized in the FPGA architecture in order to get the highest performance

and density tradeoff (Xilinx, 2000; Altera, 2001). It has arrived at the next

level of performance and complexity with the Virtex

II–Pro generation,

which has up to four hard core PowerPC core microprocessors from IBM

embedded in the matrix (Xilinx, 2001a).

As a consequence, FPGAs are increasingly demanded by spacecraft

electronic designers because of their high flexibility in achieving multiple

requirements such as high performance, low NRE (Non-Recurring

Engineering) cost and fast turnaround time. There are many types of

customization in the FPGAs. One of the most popular ones uses SRAM

memory cells to customize the FPGA, which makes possible in-the-field

customization as many times as necessary in a very short period of time.

Examples are the families Virtex

, Virtex

-E and Virtex

-II fabricated by

Xilinx. As a result, SRAM-based FPGAs are even more valuable for remote

missions by offering the additional benefits of allowing in-orbit design

changes, with the aim of reducing the mission cost by correcting errors or

improving system performance after launch.

The advantages of using SRAM-based FPGAs for space applications and

the increase of logic complexity of the programmable logic with more and

more embedded memories and specific architectures such as micro-

processors brings us the necessity of researching new SEU mitigation

techniques specific for programmable architecture. This book presents the

study and development of SEU mitigation techniques for programmable

logic architectures, more specifically for SRAM-based FPGAs. The consi-

deration of using FPGA for space applications is fairly recent, and there is a

lot of work to be done in this area. Presently, there is no efficient solution for

SRAM based FPGAs that can ensure 100% reliability in all conditions

against SEU.

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SRAM FPGA故障容错技术

A Survey of Fault Diagnosis and Fault-Tolerant Techniques 1

A Tutorial on Reed-Solomon Coding for Fault-Tolerance in RAID-like Systems

The fault-tolerance study of QCA adder based on probability model

Python framework for fault-tolerance-开源

smallrye-fault-tolerance

reference-architecture-vmware-fault-tolerance-dell-server-equallogic-iscsi_cn

microprofile-fault-tolerance:微轮廓容错

Deadlock-Free Adaptive Routing in Meshes with Fault-Tolerance Ability Based on Channel Overlapping

akka-fault-tolerance:来自 http 的容错示例

fault-tolerance-talk:这是一组与我的“容错”相关演讲相关的代码示例

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