PGA450-Q1：超声波传感器信号调节器

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"TI-PGA450-Q1.pdf 是一款由TI公司推出的超声波传感器信号调节器，主要用于停车辅助系统和物体检测应用。该器件集成了多种功能模块，如稳压器、12位SAR ADC、8位微控制器、数字带通滤波器、双通道NMOS低侧驱动器、低噪声放大器等。它还支持LIN2.1物理接口和协议，具有可配置的突发信号生成器和数字信号包络检测功能。此外，PGA450-Q1包含8K字节的OTP存储器、768字节FIFO RAM、256字节暂存RAM，以及一个四线SPI接口用于测试和编程。封装形式为TSSOP28，尺寸为9.70mm x 4.40mm。" **PGA450-Q1主要特点** 1. **集成度高**: PGA450-Q1将多个系统组件整合在一个芯片上，包括稳压器、ADC、DAC、微控制器等，大大简化了系统设计。 2. **超声波传感器接口**: 专为超声波传感器设计，能处理回声信号并计算物体距离，适合停车辅助系统。 3. ** LIN2.1接口**: 支持LIN2.1物理层和协议，可实现从设备通信，但不执行LIN唤醒功能。 4. **可配置性**: 包括可配置突发信号生成器和数字带通滤波器，允许用户根据应用需求调整参数。 5. **微控制器功能**: 内置8位微控制器，负责处理回声信号计算，提供了高度灵活的信号处理能力。 6. **电源管理**: 提供VBAT、VPWR电源输入，以及内部LIM电压限制，确保稳定工作。 7. **存储器**: 配备一次性可编程OTP存储器用于存储固件，以及FIFO RAM和暂存RAM，满足实时数据处理需求。 8. **安全特性**: 包含安全装置定时器，增加了系统安全性。 9. **封装和尺寸**: 使用TSSOP28封装，尺寸紧凑，适合空间有限的应用场景。 10. **开发支持**: 提供8K字节的开发RAM，方便用户进行软件开发和调试。 **应用场景** PGA450-Q1适用于各种需要超声波测距的应用，如汽车的倒车雷达、自动泊车系统、工业物体检测等。其强大的集成能力和灵活性使得它能在多种环境条件下稳定工作，并且通过LIN2.1接口可以方便地与其他车载电子控制单元(ECU)通信，实现系统的扩展和升级。

VPWR

See

(1)

See

(2)

See

(3)

POR release

time

(1 ms)

Power supply

monitor check

(2 ms)

See

(4)

External RAM MBIST

(5 ms)

8051 Reset

Internal Reset

PGA450-Q1

ZHCS861B –APRIL 2012–REVISED JUNE 2015

www.ti.com.cn

Feature Description (continued)

(1) The VPWR ramp reaches POR level.

(2) The internal reset to the digital core is released and EXTERNAL RAM MBIST is initiated. SPI communication is

available.

(3) 8051W reset is deasserted. Software starts execution.

(4) EXTERNAL RAM MBIST is complete. External Scratchpad RAM and FIFO RAM available for use.

Figure 8. Power-Up Waveforms

The PGA450-Q1 provides two power-control bits for enabling different analog blocks to manage the total current

consumption of the device. On power up, the device is in the QUIET mode with only the 8051W and LIN

transceiver turned on. All other analog blocks are disabled. Setting the ACTIVE_EN bit enables the low-side

drivers required for bursting as well as the echo-processing circuitry that includes the LNA and the ADC. In

addition, a separate control bit, VREG_EN, is provided to enable the VREG circuitry, which is used to charge the

external capacitor used during bursting.

The AVDD pin can be used to source current for up to 5 mA for resistive loads, including the loads on the GPIO

and Tx pins.

Table 1. Power Modes

CONTROL BIT DEFAULT FUNCTION

Enables the VREG circuitry that provides the 100-mA current to

1 VREG_EN Disabled

charge the external capacitor used during bursting

Enables the LNA, ADC, ADC REF, and other support circuitry related

2 ACTIVE_EN

(1)

Disabled

to burst generation and echo processing

(1) ACTIVE_EN bit must be set before enabling the burst / saturation or echo-enable bits.

7.3.2 VREG

The PGA450-Q1 provides a regulated voltage output which, along with an external capacitor, can be used to

drive the primary of the transformer used to excite the transducer. The VREG regulator provides a 100-mA

current, sourced from VPWR, to charge the external capacitor. The user can select the desired VREG voltage by

setting the VREG_SEL register to the appropriate value.

For VREG to be regulated to the selected voltage, VPWR must be at least 2 V above the selected VREG

voltage.

The energy required for the burst comes from the external capacitor. The device has a VREG_READY status bit

in the STATUS2 register to indicate when the capacitor is fully charged and has reached the regulation voltage.

Gate Control

Logic

2.5 V

OUTx

GND

Driver

DRAIN _MON

GATE _MON

LSG _EN

LSG

PGA450-Q1

www.ti.com.cn

ZHCS861B –APRIL 2012–REVISED JUNE 2015

NOTE

The clock synchronization feature is not available if the device is configured in SCI

buffered mode. See the LIN 2.1 Slave and Buffered SCI section for details.

7.3.4 Low-Side Drive FETs

The PGA450-Q1 provides two low-side drivers for driving the primary of a transformer or an equivalent load. The

Burst Generator section describes the control and drive modes for the low-side drive.

The low-driver block also has diagnostics. See the Diagnostics section for a description of the diagnostics.

Figure 12 shows the schematic of the low-side drive

Figure 12. Low-Side Drive Block Diagram

7.3.5 Burst Generator

The burst generator block generates the high-frequency pulses used to drive the gates of the low-side FETs. The

low-side FETs ultimately drive the transducer by modulating the primary of the transformer.

The PGA450-Q1 provides mode bits in the BURST MODE register (see the Burst Mode Register (offset = 0xB3)

[reset = 0] section) to configure each low-side drive MOSFET in three possible drive modes.

The three possible drive modes are:

Single-ended: In this mode, one low-side switch is used to turn current on and off in the primary of the

transformer. The rate of change of current in the primary generates a voltage in the secondary of

the transformer, which is connected to the transducer.

Push-pull: In this mode, two low-side switches are used to turn current on and off in two primary coils in the

transformer. The primary coils have the same number of turns. The rate of change of current in the

primary generates a voltage in the secondary of the transformer, which is connected to the

transducer. The direction of current in the secondary generates voltages of opposite polarity in the

secondary, effectively doubling the peak-to-peak voltage in the secondary.

8051W port drive:In this mode, the low-side switches are controlled through the an 8051W port pin.

Figure 13 shows the block diagram of the burst generator. The figure shows that the burst generator has a

number of registers which the user software must configure.

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