STM32F103ZG：高性能XL密度32位微控制器技术规格

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"STM32F103ZG是一款由STMicroelectronics生产的高性能微控制器，属于STM32F103系列的XL密度性能线产品。该芯片基于ARM Cortex-M3 CPU，具备MPU（内存保护单元），拥有768KB至1MB的闪存、96KB的SRAM，并且支持多种外设接口，如USB、CAN、17个定时器、3个ADC和13种通信接口。" STM32F103ZG的关键特性包括： 1. **核心处理器**：采用32位ARM Cortex-M3内核，最高运行频率达到72MHz，能在0等待状态访问内存时实现1.25 DMIPS/MHz的性能。CPU还包括单周期乘法器和硬件除法器，提高了计算效率。 2. **存储器**：内置768KB到1MB的闪存和96KB的SRAM，满足不同存储需求。此外，还配备灵活的静态存储器控制器，支持4个Chip Select，可连接CompactFlash、SRAM、PSRAM、NOR和NAND等不同类型内存。同时，芯片还提供了LCD并行接口，支持8080和6800模式。 3. **时钟、复位和电源管理**：工作电压范围在2.0V到3.6V之间，具有上电复位(POR)、掉电复位(PDR)和可编程电压检测器(PVD)功能。支持4至16MHz的晶体振荡器，内置8MHz的工厂校准RC振荡器和40kHz的校准RC振荡器，为实时时钟(RTC)提供32kHz振荡器。 4. **低功耗模式**：设计有睡眠、停止和待机三种低功耗模式，以及VBAT供电，以支持RTC和备用电源的需求。 5. **丰富的外设**：包括USB接口、CAN总线接口，17个定时器可以用于各种计时和控制任务，3个模拟数字转换器(ADC)用于信号采集，以及13种不同的通信接口，如I2C、SPI和UART等，这使得STM32F103ZG适用于广泛的嵌入式应用。 6. **温度和规格**：这个预发布的产品信息可能随时间而变更，具体以最新的数据手册为准。 STM32F103ZG因其强大的处理能力、丰富的外设和低功耗特性，广泛应用于工业控制、物联网设备、智能家居、消费电子等领域。开发人员可以通过其灵活的外设配置，设计出满足特定需求的嵌入式解决方案。在实际应用中，配合适当的开发工具和软件库，能够简化开发流程，提高项目效率。

Description STM32F103xF, STM32F103xG

16/120 Doc ID 16554 Rev 3

2.3.5 Embedded SRAM

96 Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0 wait states.

2.3.6 FSMC (flexible static memory controller)

The FSMC is embedded in the STM32F103xF and STM32F103xG performance line family.

It has four Chip Select outputs supporting the following modes: PC Card/Compact Flash,

SRAM, PSRAM, NOR and NAND.

Functionality overview:

● The three FSMC interrupt lines are ORed in order to be connected to the NVIC

● Write FIFO

● Code execution from external memory except for NAND Flash and PC Card

● The targeted frequency, f

CLK

, is HCLK/2, so external access is at 36 MHz when HCLK

is at 72 MHz and external access is at 24 MHz when HCLK is at 48 MHz

2.3.7 LCD parallel interface

The FSMC can be configured to interface seamlessly with most graphic LCD controllers. It

supports the Intel 8080 and Motorola 6800 modes, and is flexible enough to adapt to

specific LCD interfaces. This LCD parallel interface capability makes it easy to build cost-

effective graphic applications using LCD modules with embedded controllers or high-

performance solutions using external controllers with dedicated acceleration.

2.3.8 Nested vectored interrupt controller (NVIC)

The STM32F103xF and STM32F103xG performance line embeds a nested vectored

interrupt controller able to handle up to 60 maskable interrupt channels (not including the 16

interrupt lines of Cortex™-M3) and 16 priority levels.

● Closely coupled NVIC gives low latency interrupt processing

● Interrupt entry vector table address passed directly to the core

● Closely coupled NVIC core interface

● Allows early processing of interrupts

● Processing of late arriving higher priority interrupts

● Support for tail-chaining

● Processor state automatically saved

● Interrupt entry restored on interrupt exit with no instruction overhead

This hardware block provides flexible interrupt management features with minimal interrupt

latency.

2.3.9 External interrupt/event controller (EXTI)

The external interrupt/event controller consists of 19 edge detector lines used to generate

interrupt/event requests. Each line can be independently configured to select the trigger

event (rising edge, falling edge, both) and can be masked independently. A pending register

maintains the status of the interrupt requests. The EXTI can detect an external line with a

pulse width shorter than the Internal APB2 clock period. Up to 112 GPIOs can be connected

to the 16 external interrupt lines.

STM32F103xF, STM32F103xG Description

Doc ID 16554 Rev 3 17/120

2.3.10 Clocks and startup

System clock selection is performed on startup, however the internal RC 8 MHz oscillator is

selected as default CPU clock on reset. An external 4-16 MHz clock can be selected, in

which case it is monitored for failure. If failure is detected, the system automatically switches

back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full

interrupt management of the PLL clock entry is available when necessary (for example with

failure of an indirectly used external oscillator).

Several prescalers allow the configuration of the AHB frequency, the high speed APB

(APB2) and the low speed APB (APB1) domains. The maximum frequency of the AHB and

the high speed APB domains is 72 MHz. The maximum allowed frequency of the low speed

APB domain is 36 MHz. See

Figure 2 for details on the clock tree.

2.3.11 Boot modes

At startup, boot pins are used to select one of three boot options:

● Boot from user Flash: you have an option to boot from any of two memory banks. By

default, boot from Flash memory bank 1 is selected. You can choose to boot from Flash

memory bank 2 by setting a bit in the option bytes.

● Boot from system memory

● Boot from embedded SRAM

The boot loader is located in system memory. It is used to reprogram the Flash memory by

using USART1.

2.3.12 Power supply schemes

● V

= 2.0 to 3.6 V: external power supply for I/Os and the internal regulator.

Provided externally through V

pins.

● V

SSA

, V

DDA

= 2.0 to 3.6 V: external analog power supplies for ADC, DAC, Reset blocks,

RCs and PLL (minimum voltage to be applied to VDDA is 2.4 V when the ADC or DAC

is used). V

DDA

and V

SSA

must be connected to V

and V

, respectively.

● V

BAT

= 1.8 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and backup

registers (through power switch) when V

is not present.

For more details on how to connect power pins, refer to Figure 10: Power supply scheme.

2.3.13 Power supply supervisor

The device has an integrated power-on reset (POR)/power-down reset (PDR) circuitry. It is

always active, and ensures proper operation starting from/down to 2 V. The device remains

in reset mode when V

is below a specified threshold, V

POR/PDR

, without the need for an

external reset circuit.

The device features an embedded programmable voltage detector (PVD) that monitors the

DDA

power supply and compares it to the V

PVD

threshold. An interrupt can be

generated when V

DDA

drops below the V

PVD

threshold and/or when V

DDA

is higher

than the V

PVD

threshold. The interrupt service routine can then generate a warning

message and/or put the MCU into a safe state. The PVD is enabled by software. Refer to

Table 12: Embedded reset and power control block characteristics for the values of

POR/PDR

and V

PVD

Description STM32F103xF, STM32F103xG

18/120 Doc ID 16554 Rev 3

2.3.14 Voltage regulator

The regulator has three operation modes: main (MR), low power (LPR) and power down.

● MR is used in the nominal regulation mode (Run)

● LPR is used in the Stop modes.

● Power down is used in Standby mode: the regulator output is in high impedance: the

kernel circuitry is powered down, inducing zero consumption (but the contents of the

registers and SRAM are lost)

This regulator is always enabled after reset. It is disabled in Standby mode.

2.3.15 Low-power modes

The STM32F103xF and STM32F103xG performance line supports three low-power modes

to achieve the best compromise between low power consumption, short startup time and

available wakeup sources:

● Sleep mode

In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can

wake up the CPU when an interrupt/event occurs.

● Stop mode

Stop mode achieves the lowest power consumption while retaining the content of

SRAM and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI RC

and the HSE crystal oscillators are disabled. The voltage regulator can also be put

either in normal or in low-power mode.

The device can be woken up from Stop mode by any of the EXTI line. The EXTI line

source can be one of the 16 external lines, the PVD output, the RTC alarm or the USB

wakeup.

● Standby mode

The Standby mode is used to achieve the lowest power consumption. The internal

voltage regulator is switched off so that the entire 1.8 V domain is powered off. The

PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering

Standby mode, SRAM and register contents are lost except for registers in the Backup

domain and Standby circuitry.

The device exits Standby mode when an external reset (NRST pin), an IWDG reset, a

rising edge on the WKUP pin, or an RTC alarm occurs.

Note: The RTC, the IWDG, and the corresponding clock sources are not stopped by entering Stop

or Standby mode.

2.3.16 DMA

The flexible 12-channel general-purpose DMAs (7 channels for DMA1 and 5 channels for

DMA2) are able to manage memory-to-memory, peripheral-to-memory and memory-to-

peripheral transfers. The two DMA controllers support circular buffer management,

removing the need for user code intervention when the controller reaches the end of the

buffer.

Each channel is connected to dedicated hardware DMA requests, with support for software

trigger on each channel. Configuration is made by software and transfer sizes between

source and destination are independent.

STM32F103xF, STM32F103xG Description

Doc ID 16554 Rev 3 19/120

The DMA can be used with the main peripherals: SPI, I

C, USART, general-purpose, basic

and advanced-control timers TIMx, DAC, I

S, SDIO and ADC.

2.3.17 RTC (real-time clock) and backup registers

The RTC and the backup registers are supplied through a switch that takes power either on

supply when present or through the V

BAT

pin. The backup registers are forty-two 16-bit

registers used to store 84 bytes of user application data when V

power is not present.

They are not reset by a system or power reset, and they are not reset when the device

wakes up from the Standby mode.

The real-time clock provides a set of continuously running counters which can be used with

suitable software to provide a clock calendar function, and provides an alarm interrupt and a

periodic interrupt. It is clocked by a 32.768 kHz external crystal, resonator or oscillator, the

internal low power RC oscillator or the high-speed external clock divided by 128. The

internal low-speed RC has a typical frequency of 40 kHz. The RTC can be calibrated using

an external 512 Hz output to compensate for any natural quartz deviation. The RTC features

a 32-bit programmable counter for long term measurement using the Compare register to

generate an alarm. A 20-bit prescaler is used for the time base clock and is by default

configured to generate a time base of 1 second from a clock at 32.768 kHz.

2.3.18 Timers and watchdogs

The XL-density STM32F103xx performance line devices include up to two advanced-control

timers, up to ten general-purpose timers, two basic timers, two watchdog timers and a

SysTick timer.

Table 4 compares the features of the advanced-control, general-purpose and basic timers.

Table 4. STM32F103xF and STM32F103xG timer feature comparison

Timer

Counter

resolution

Counter

type

Prescaler factor

DMA request

generation

Capture/compare

channels

Complementary

outputs

TIM1, TIM8 16-bit

Up,

down,

up/down

Any integer between

1 and 65536

Ye s 4 Ye s

TIM2, TIM3,

TIM4, TIM5

16-bit

Up,

down,

up/down

Any integer between

1 and 65536

Ye s 4 N o

TIM9, TIM12 16-bit Up

Any integer between

1 and 65536

No 2 No

TIM10, TIM11

TIM13, TIM14

16-bit Up

Any integer between

1 and 65536

No 1 No

TIM6, TIM7 16-bit Up

Any integer between

1 and 65536

Ye s 0 N o

Description STM32F103xF, STM32F103xG

20/120 Doc ID 16554 Rev 3

Advanced-control timers (TIM1 and TIM8)

The two advanced-control timers (TIM1 and TIM8) can each be seen as a three-phase

PWM multiplexed on 6 channels. They have complementary PWM outputs with

programmable inserted dead-times. They can also be seen as a complete general-purpose

timer. The 4 independent channels can be used for:

● Input capture

● Output compare

● PWM generation (edge or center-aligned modes)

● One-pulse mode output

If configured as a standard 16-bit timer, it has the same features as the TIMx timer. If

configured as the 16-bit PWM generator, it has full modulation capability (0-100%).

In debug mode, the advanced-control timer counter can be frozen and the PWM outputs

disabled to turn off any power switch driven by these outputs.

Many features are shared with those of the general-purpose TIM timers which have the

same architecture. The advanced-control timer can therefore work together with the TIM

timers via the Timer Link feature for synchronization or event chaining.

General-purpose timers (TIMx)

There are10 synchronizable general-purpose timers embedded in the STM32F103xF and

STM32F103xG performance line devices (see

Table 4 for differences).

● TIM2, TIM3, TIM4, TIM5

There are up to 4 synchronizable general-purpose timers (TIM2, TIM3, TIM4 and TIM5)

embedded in the STM32F103xF and STM32F103xG access line devices.

These timers are based on a 16-bit auto-reload up/down counter, a 16-bit prescaler

and feature 4 independent channels each for input capture/output compare, PWM or

one-pulse mode output. This gives up to 16 input captures / output compares / PWMs

on the largest packages.

Their counter can be frozen in debug mode. Any of the general-purpose timers can be

used to generate PWM outputs. They all have independent DMA request generation.

These timers are capable of handling quadrature (incremental) encoder signals and the

digital outputs from 1 to 3 hall-effect sensors.

● TIM10, TIM11 and TIM9

These timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler.

TIM10 and TIM11 feature one independent channel, whereas TIM9 has two

independent channels for input capture/output compare, PWM or one-pulse mode

output. They can be synchronized with the TIM2, TIM3, TIM4, TIM5 full-featured

general-purpose timers. They can also be used as simple time bases.

● TIM13, TIM14 and TIM12

These timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler.

TIM13 and TIM14 feature one independent channel, whereas TIM12 has two

independent channels for input capture/output compare, PWM or one-pulse mode

output. They can be synchronized with the TIM2, TIM3, TIM4, TIM5 full-featured

general-purpose timers. They can also be used as simple time bases.

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STM32F103ZG：高性能XL密度32位微控制器技术规格

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